configure.ac | 2 +-
src/via_display.c | 17 +++++++++++++++++
2 files changed, 18 insertions(+), 1 deletion(-)
New commits:
commit 0874c7e40a8aa570c2a2b96d5c8950c2aba4f0f6
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Thu Jun 9 23:04:24 2016 -0500
Version bumped to 0.4.174
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/configure.ac b/configure.ac
index ea6ba2e..9985324 100644
--- a/configure.ac
+++ b/configure.ac
@@ -23,7 +23,7 @@
# Initialize Autoconf
AC_PREREQ(2.57)
AC_INIT([xf86-video-openchrome],
- [0.4.173],
+ [0.4.174],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg&component=Driver/openchrome],
[xf86-video-openchrome])
commit 1ffcaaa2535172d2ab47d7bd4c0da55cdb6c6d98
Author: Kevin Brace <kevinbr...@gmx.com>
Date: Thu Jun 9 23:00:54 2016 -0500
Setting DVP1 clock and data drive strength to the highest
VIA frame buffer device driver was doing this, we will do it, too.
Signed-off-by: Kevin Brace <kevinbr...@gmx.com>
diff --git a/src/via_display.c b/src/via_display.c
index 7aa25a6..e70ee6f 100644
--- a/src/via_display.c
+++ b/src/via_display.c
@@ -312,6 +312,9 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
temp = hwp->readSeq(hwp, 0x3F);
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"SR3F: 0x%02X\n", temp));
+ temp = hwp->readSeq(hwp, 0x65);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR65: 0x%02X\n", temp));
temp = hwp->readCrtc(hwp, 0x36);
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"CR36: 0x%02X\n", temp));
@@ -509,6 +512,20 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
* 11: Clock on/off according to each engine IDLE status */
ViaSeqMask(hwp, 0x3F, 0xFF, 0xFF);
+ /* Set DVP1 data drive strength to 0b11 (highest). */
+ /* Set DVP1 clock drive strength to 0b11 (highest). */
+ /* 3C5.65[3:2] - DVP1 Clock Pads Driving Select
+ * 00: lowest
+ * 01: low
+ * 10: high
+ * 11: highest
+ * 3C5.65[1:0] - DVP1 Data Pads Driving Select
+ * 00: lowest
+ * 01: low
+ * 10: high
+ * 11: highest */
+ ViaSeqMask(hwp, 0x65, 0x0F, 0x0F);
+
/* 3X5.36[7] - DPMS VSYNC Output
* 3X5.36[6] - DPMS HSYNC Output
* 3X5.36[5:4] - DPMS Control
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