On Thu, Aug 4, 2016 at 5:29 PM, Andi <[email protected]> wrote: > > >> > This sounds like a SPARK-architecture could do it. SPARC T5 > <http://www.oracle.com/us/corporate/innovation/sparc-t5-deep-dive/index.html> >
Please re-read and re-think. The Sparc architecture is just another RISC superscalar architecture, not really or fundamentally different than MIPS or POWER, or even the risc superscalar core inside of the Intel x86 chips. The primary difference is that the Sparc has a big register file and a register window, used for the C/C++/Java stack push and pop, whereas the other arches use those transistors register scoreboarding, coloring and so on. https://en.wikipedia.org/wiki/Superscalar_processor https://en.wikipedia.org/wiki/Reduced_instruction_set_computing https://en.wikipedia.org/wiki/SPARC https://en.wikipedia.org/wiki/Scoreboarding Again, the problem is how to traverse rhizomes quickly and efficiently, given the non-locality of memory access. --linas -- You received this message because you are subscribed to the Google Groups "opencog" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected]. Visit this group at https://groups.google.com/group/opencog. To view this discussion on the web visit https://groups.google.com/d/msgid/opencog/CAHrUA365as6mn0ROrM4E%2BS2VoYCKJsoc0tn3h%3DJWW4u_hwV%2BHw%40mail.gmail.com. For more options, visit https://groups.google.com/d/optout.
