O.K. ty linas! Am Freitag, 5. August 2016 00:53:59 UTC+2 schrieb linas: > > > > On Thu, Aug 4, 2016 at 5:29 PM, Andi <[email protected] <javascript:>> > wrote: > >> >> >>> >> This sounds like a SPARK-architecture could do it. SPARC T5 >> <http://www.oracle.com/us/corporate/innovation/sparc-t5-deep-dive/index.html> >> > > Please re-read and re-think. The Sparc architecture is just another RISC > superscalar architecture, not really or fundamentally different than MIPS > or POWER, or even the risc superscalar core inside of the Intel x86 chips. > The primary difference is that the Sparc has a big register file and a > register window, used for the C/C++/Java stack push and pop, whereas the > other arches use those transistors register scoreboarding, coloring and so > on. > > https://en.wikipedia.org/wiki/Superscalar_processor > https://en.wikipedia.org/wiki/Reduced_instruction_set_computing > https://en.wikipedia.org/wiki/SPARC > https://en.wikipedia.org/wiki/Scoreboarding > > > Again, the problem is how to traverse rhizomes quickly and efficiently, > given the non-locality of memory access. > > --linas > > >
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