This series contains a set of a recipes for Open Source FPGA tools which
provide a full Verilog to target Bitstream flow for the Lattice iCE40
FPGAs.

This includes the following tools:
 * Yosys - Synthesis
 * Arachne-PNR - Place and Route
 * IceStorm - Bitmapping and JTAG programming

Also included in the series is Icarus Verilog which is useful for
simulation of Verilog designs.

All recipes in the series have been tested on native (x86-64),
nativesdk (x86-64) and target (armv5/qemuarm). With a relatively complex
Verilog design (for iCE40).

For a sample recipe that makes use of these tools within bitbake see:
  
https://github.com/nathanrossi/gps-clock-project/blob/master/meta-gps-clock/recipes/display-controller/display-controller.bb

Please note whilst this series is sent for oe-core it may be better
located in another layer? (e.g. meta-oe). However since the recipes and
the tools they build are not specific to a single BSP it did not make
sense to keep in a BSP specific layer.

Nathan Rossi (4):
  yosys: Add Yosys and ABC recipes
  icestorm: Add IceStorm tools for iCE40 FPGAs
  arachne-pnr: Add Arachne Place and route for iCE40 FPGAs
  icarus-verilog: Add Icarus Verilog recipe

 .../arachne-pnr/arachne-pnr_git.bb                 | 44 +++++++++++++++++
 .../icarus-verilog/icarus-verilog_git.bb           | 33 +++++++++++++
 meta/recipes-devtools/icestorm/icestorm_git.bb     | 51 ++++++++++++++++++++
 meta/recipes-devtools/yosys/berkeley-abc_git.bb    | 30 ++++++++++++
 meta/recipes-devtools/yosys/yosys_git.bb           | 55 ++++++++++++++++++++++
 5 files changed, 213 insertions(+)
 create mode 100644 meta/recipes-devtools/arachne-pnr/arachne-pnr_git.bb
 create mode 100644 meta/recipes-devtools/icarus-verilog/icarus-verilog_git.bb
 create mode 100644 meta/recipes-devtools/icestorm/icestorm_git.bb
 create mode 100644 meta/recipes-devtools/yosys/berkeley-abc_git.bb
 create mode 100644 meta/recipes-devtools/yosys/yosys_git.bb

-- 
2.14.1
-- 
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