Yosys provides a Open Source Verilog synthesis flow for a number of targets including Altera, ASIC flows, Lattice FPGAs/CPLDs, Xilinx, etc. This tool provides the first step in a fully open source HDL/Verilog to bitstream flow.
Also included is its primary dependency Berkeley ABC which is used for the synthesis and formal verification tooling. Signed-off-by: Nathan Rossi <[email protected]> --- meta/recipes-devtools/yosys/berkeley-abc_git.bb | 30 ++++++++++++++ meta/recipes-devtools/yosys/yosys_git.bb | 55 +++++++++++++++++++++++++ 2 files changed, 85 insertions(+) create mode 100644 meta/recipes-devtools/yosys/berkeley-abc_git.bb create mode 100644 meta/recipes-devtools/yosys/yosys_git.bb diff --git a/meta/recipes-devtools/yosys/berkeley-abc_git.bb b/meta/recipes-devtools/yosys/berkeley-abc_git.bb new file mode 100644 index 0000000000..8f39c7ab29 --- /dev/null +++ b/meta/recipes-devtools/yosys/berkeley-abc_git.bb @@ -0,0 +1,30 @@ +DESCRIPTION = "Berkeley ABC: System for Sequential Logic Synthesis and Formal Verification" +HOMEPAGE = "http://www.eecs.berkeley.edu/~alanmi/abc/"; +# License is MIT, but differs from standard license text +LICENSE = "MIT" +SECTION = "devel/hardware" + +LIC_FILES_CHKSUM = "file://copyright.txt;md5=04eb1ba7f36d87b164b6224e5417b860" + +SRC_URI = "hg://bitbucket.org/alanmi/abc;protocol=https;branch=default;module=root" +SRCREV = "ff5be06" + +S = "${WORKDIR}/root" + +PV = "1.01+hg${SRCPV}" + +DEPENDS = "readline" + +# set the ARCHFLAGS to avoid execution of arch_flags during build +ABC_ARCHFLAGS_x86-64 = "-DLIN64 -DSIZEOF_VOID_P=8 -DSIZEOF_LONG=8 -DSIZEOF_INT=4" +ABC_ARCHFLAGS = "-DLIN -DSIZEOF_VOID_P=4 -DSIZEOF_LONG=4 -DSIZEOF_INT=4 -fpermissive -w" + +do_compile() { + oe_runmake ABC_MAKE_VERBOSE=1 ARCHFLAGS="${ABC_ARCHFLAGS}" CC="${CXX}" CXX="${CXX}" LD="${CXX} ${LDFLAGS}" +} + +do_install() { + install -Dm 755 ${B}/abc ${D}${bindir}/abc +} + +BBCLASSEXTEND = "native nativesdk" diff --git a/meta/recipes-devtools/yosys/yosys_git.bb b/meta/recipes-devtools/yosys/yosys_git.bb new file mode 100644 index 0000000000..06ae74052a --- /dev/null +++ b/meta/recipes-devtools/yosys/yosys_git.bb @@ -0,0 +1,55 @@ +DESCRIPTION = "Yosys, a framework for Verilog RTL synthesis" +HOMEPAGE = "http://www.clifford.at/yosys/"; +LICENSE = "ISC" +SECTION = "devel/verilog" + +LIC_FILES_CHKSUM = "file://README.md;beginline=2;endline=16;md5=ed95f8bf65484f10d063cb460b4df728" + +SRC_URI = "git://github.com/cliffordwolf/yosys;protocol=https" +SRCREV = "7d41c5e1770419369617011167f01112d9b9b436" + +S = "${WORKDIR}/git" + +PV = "0.7+git${SRCPV}" + +inherit pkgconfig + +DEPENDS = " \ + python3-native \ + bison-native \ + flex-native \ + gawk-native \ + tcl-native \ + berkeley-abc \ + readline \ + tcl \ + libffi \ + " + +RDEPENDS_${PN} += "berkeley-abc bash" + +# OE modifies target tcl to populate includes into subdirectory but never sets that up in .pc +CXXFLAGS_append = " -I=${includedir}/tcl8.6" + +do_configure_append () { + # config build for GCC + make config-gcc + + # remove posions + sed -i 's/-I$(PREFIX)\/include//g' ${S}/Makefile + sed -i 's/-L$(LIBDIR)//g' ${S}/Makefile +} + +# use abc from PATH +export ABCEXTERNAL = "abc" + +do_compile() { + # force make variables for CXX and LD, the makefile forces them instead of defaulting + oe_runmake PREFIX="${prefix}" PRETTY=0 CXX="${CXX}" LD="${CC}" +} + +do_install() { + oe_runmake PREFIX="${prefix}" PRETTY=0 DESTDIR="${D}" install +} + +BBCLASSEXTEND = "native nativesdk" -- 2.14.1 -- _______________________________________________ Openembedded-core mailing list [email protected] http://lists.openembedded.org/mailman/listinfo/openembedded-core
