On Sun, Oct 25, 2026 at 8:17 AM Mark Hatle via lists.openembedded.org <[email protected]> wrote:
> > > On 10/25/26 1:56 AM, Khem Raj via lists.openembedded.org wrote: > > QB_CPU defaults to rva23s64, which mandates V, but linux-yocto only > > enables CONFIG_RISCV_ISA_V when TUNE_FEATURES contains 'v', and > > riscv-isa-clear.scc turns it off otherwise. With the default rv64gc > > tune the kernel therefore runs without V support and any userspace > > vector instruction raises SIGILL, even code that selects RVV at > > runtime. > > > > Append riscv-isa-v.scc to KERNEL_FEATURES_RISCV so it lands after > > riscv-isa-clear.scc. Userspace keeps the rv64gc tune and stays > > portable; the kernel detects V at boot, so this is harmless on CPUs > > without it. > > This doesn't make sense to me. If we want a default configuration to > include > vector, then we need to select an ISA that includes vector extensions. > Yes, at this point, we do not have many SBCs which is using rva23gv ISA except k3 maybe handful of others, so changing qemu defaults to use RVV by default will mean we are not covering the current widely used ISA as default but there are packages which need vectorization. So its enabling rvv in kernel but keeps the userspace ABI to still be rv64gc. Bumping default tune for qemuriscv64 to use rv64gcv is straight forward however, it does mean coverage moves to rva23 and newer. I am fine with this as well. would be good for others to chime in. > > Same with userspace, if anything is using vector instructions it should be > using > a vector based tune. > > --Mark > > > Signed-off-by: Khem Raj <[email protected]> > > --- > > meta/conf/machine/qemuriscv64.conf | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/meta/conf/machine/qemuriscv64.conf > b/meta/conf/machine/qemuriscv64.conf > > index a753af0576..0aacfa378f 100644 > > --- a/meta/conf/machine/qemuriscv64.conf > > +++ b/meta/conf/machine/qemuriscv64.conf > > @@ -6,6 +6,11 @@ require conf/machine/include/riscv/qemuriscv.inc > > > > XVISOR_PLAT = "riscv/virt64" > > > > +# The default QB_CPU (rva23s64) has the Vector extension, so enable it > in the > > +# kernel even though the default tune is rv64gc, userspace can then use > V at > > +# runtime. Appending here places it after riscv-isa-clear.scc, which > disables V. > > +KERNEL_FEATURES_RISCV:append = " arch/riscv/tunes/riscv-isa-v.scc" > > + > > EXTRA_IMAGEDEPENDS += "u-boot" > > UBOOT_MACHINE = "qemu-riscv64_smode_defconfig" > > UBOOT_ELF = "u-boot" > > > > > > > > > > > > > >
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