> - struct ipoib_rx_buf *rx_ring; > + struct ipoib_rx_buf *rx_ring ____cacheline_aligned_in_smp; > > spinlock_t tx_lock; > - struct ipoib_tx_buf *tx_ring; > + struct ipoib_tx_buf *tx_ring ____cacheline_aligned_in_smp; > unsigned tx_head; > unsigned tx_tail; > struct ib_sge tx_sge; > struct ib_send_wr tx_wr; > > - struct ib_wc ibwc[IPOIB_NUM_WC]; > + struct ib_wc send_ibwc[IPOIB_NUM_SEND_WC] > ____cacheline_aligned_in_smp; > + struct ib_wc recv_ibwc[IPOIB_NUM_RECV_WC] > ____cacheline_aligned_in_smp;
This doesn't look right. It puts tx_lock in the same cacheline as rx_ring, and then puts send_ibwc and recv_ibwc in completely different cachelines. Wouldn't it make more sense to sort the rx and tx stuff so that they're each in as few non-shared cachelines as possible? - R. _______________________________________________ openib-general mailing list [email protected] http://openib.org/mailman/listinfo/openib-general To unsubscribe, please visit http://openib.org/mailman/listinfo/openib-general
