At 03:23 PM 8/25/2006, Greg Lindahl wrote:
>On Fri, Aug 25, 2006 at 03:21:20PM -0400, [EMAIL PROTECTED] wrote:
>
>> I presume you meant invalidate the cache, not flush it, before
>accessing DMA'ed
>> data.
>
>Yes, this is what I meant. Sorry!
Flush (sync for_device) before posting.
Invalidate (sync for_cpu) before processing.
On some architectures, these operations flush and/or invalidate
i/o pipeline caches as well. As they should.
Many platforms have coherent I/O components so the explicit requirements on software to participate are often eliminated.
Mike
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