[PATCH] s3c2410 gpio in qemu-neo1973

[Salil Bijur]

Hello,

I noticed the code in qemu-neo1973 to set external interrupts via gpio pins.

switch ((s->extint[e] >> (line * 3)) & 7)
This check assumes that the EINTn register has contiguous sets of 3
bits for signalling method [0-2, 3-5, 6-8, etc].

But I took a look at the user manual of s3c2410 and it seems to be
different. There are sets of 3 bits followed by a reserved bit so the
signalling methods are in bits [0-2, 4-6, 8-10, etc.].
So the correct logic in the switch case should be:
switch ((s->extint[e] >> ((line * 4) - 1)) & 7)

Attaching a patch that hopefully corrects this.

Thanks,
Salil

diff --git a/hw/s3c24xx_gpio.c b/hw/s3c24xx_gpio.c
index de8dfb0..dff9b21 100644
--- a/hw/s3c24xx_gpio.c
+++ b/hw/s3c24xx_gpio.c
@@ -83,7 +83,7 @@ static void s3c_gpio_set(void *opaque, int line, int level)
         }
         if (level) {
             if (!((s->bank[bank].dat >> line) & 1))
-                switch ((s->extint[e] >> (line * 3)) & 7) {
+                switch ((s->extint[e] >> ((line * 4) - 1)) & 7) {
                 case 1:
                 case 4 ... 7:
                     s3c_gpio_extint(s, eint);
@@ -92,7 +92,7 @@ static void s3c_gpio_set(void *opaque, int line, int level)
             s->bank[bank].dat |= 1 << line;
         } else {
             if ((s->bank[bank].dat >> line) & 1)
-                switch ((s->extint[e] >> (line * 3)) & 7) {
+		switch ((s->extint[e] >> ((line * 4) - 1)) & 7) {
                 case 1:
                 case 4 ... 5:
                     break;