-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Somebody in the thread at some point said:
>> If there is no objection maybe we could try 12pF or somesuch there >> instead of 47pF. But at this time near production I can imagine the >> urge is to let all sleeping dogs lie. > From LCM-datasheet: > abs. max. ratings: (for PCLK, @VDDIO=3,0V) > VInput-Low: <= VDDIO * 0,3 = 0,9V > VInput-High:>= VDDIO * 0,7 = 2,1V > > I think this scope-plot signals really critical situation for PCLK. > NB: with higher clock freq , situation gets worse! That is a very good point, Joerg :-/ Also with this kind of distortion, after the input buffer you can run into duty cycle changes (since the region above or below the threshold is the tip of the triangle) which on some designs is fatal. Evidently it is pretty accepting of weird PCLK but yours is a good reason to at least consider reducing that cap. - -Andy -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.7 (GNU/Linux) Comment: Using GnuPG with Fedora - http://enigmail.mozdev.org iD8DBQFH1VyZOjLpvpq7dMoRApfUAKCPCUfhc72BLh/87opANZDIJsH0bACaA4Oy ESp2w7duZmmCZhTxvupL6zs= =E926 -----END PGP SIGNATURE-----
