Hi list,
I'm currently implementing a test interface/ICE for ZPU-based processor, and I
wish to add support in OpenOCD for it, and I have no clue where to start ;)
Right now what I have is:
a) Full GCC and GDB implementation working.
b) CPU support for debug mode, opcode injection, register/state
inspection, single-stepping and soft breakpoints.
Other thing I might need is to cascade JTAG interfaces. On some FPGA you have
access to some boundary-scan elements, which allows you to kinda use the same
JTAG
interface as the FPGA itself to debug the on-chip logic, in order to reduce
overhead. So what I need is to actually put a JTAG adaptor accessing another
JTAG
adaptor, which itself accesses the CPU.
For Xilinx FPGA, which have 2 user-configurable chains, I use the first one as
an instruction register, and the second one as the data register. One can
emulate
a typical TAP with these two chains.
Adding the controller for these chains is easy, but requires it to be connected
to the main JTAG adaptor.
It's hard for me not to have this kind of controller, for I don't actually have
a JTAG cable (although I could use a FTDI2232 interface if needed).
Any help about the two items would be very welcomed.
Best,
Álvaro Lopes
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