Hi again,
I decided to move on, and given a clue about remote bitbanging interface
support in OpenOCD, I wrote a small server for it and integrated it with GHDL
simulation engine, exposing a "pure" JTAG interface which can be then connected
to a TAP controller and used during simulation.
So far things seem to work OK, I created a JTAG TAP and implemented an IR
(4-bit) register and IDCODE (32-bit). IDCODE is being set to x"deadbeef", and it
correctly shows up on OpenOCD (the board used below is only for connection
testing)
$ openocd -f interface/remote-bitbang.cfg -f board/zy1000.cfg
Open On-Chip Debugger 0.6.0-dev-00293-gc132304-dirty (2012-01-03-10:57)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.sourceforge.net/doc/doxygen/bugs.html
Warn : Adapter driver 'remote_bitbang' did not declare which transports it
allows; assuming legacy JTAG-only
Info : only one transport option; autoselect 'jtag'
srst_only srst_pulls_trst srst_gates_jtag srst_open_drain
fast memory access is enabled
dcc downloads are enabled
16000 kHz
production_test
Info : Initializing remote_bitbang driver
Info : Connecting to localhost:7264
Info : remote_bitbang driver initialized
Info : clock speed 1 kHz
Info : JTAG tap: zy1000.cpu tap/device found: 0xdeadbeef (mfg: 0x777, part:
0xeadb, ver: 0xd)
Warn : JTAG tap: zy1000.cpu UNEXPECTED: 0xdeadbeef (mfg: 0x777, part:
0xeadb, ver: 0xd)
Error: JTAG tap: zy1000.cpu expected 1 of 1: 0x1f0f0f0f (mfg: 0x787, part:
0xf0f0, ver: 0x1)
Now, I'd really would like some help about where to look for CPU/BOARD/JTAG
definitions, in order to start the real work.
PS: If anyone is interested on this OpenOCD->remote bitbang->GHDL->JTAG please
let me know.
Best,
Álvaro
Álvaro Lopes wrote:
> Hi list,
>
> I'm currently implementing a test interface/ICE for ZPU-based processor, and
> I wish to add support in OpenOCD for it, and I have no clue where to start ;)
>
> Right now what I have is:
>
> a) Full GCC and GDB implementation working.
> b) CPU support for debug mode, opcode injection, register/state
> inspection, single-stepping and soft breakpoints.
>
> Other thing I might need is to cascade JTAG interfaces. On some FPGA you have
> access to some boundary-scan elements, which allows you to kinda use the same
> JTAG
> interface as the FPGA itself to debug the on-chip logic, in order to reduce
> overhead. So what I need is to actually put a JTAG adaptor accessing another
> JTAG
> adaptor, which itself accesses the CPU.
> For Xilinx FPGA, which have 2 user-configurable chains, I use the first one
> as an instruction register, and the second one as the data register. One can
> emulate
> a typical TAP with these two chains.
>
> Adding the controller for these chains is easy, but requires it to be
> connected to the main JTAG adaptor.
>
> It's hard for me not to have this kind of controller, for I don't actually
> have a JTAG cable (although I could use a FTDI2232 interface if needed).
>
> Any help about the two items would be very welcomed.
>
> Best,
> Álvaro Lopes
>
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