http://www.gnu.org/software/grep/
You are slowly getting there, but you'll have to grep more ;)

On Fri, Feb 10, 2012 at 8:44 PM,  <[email protected]> wrote:
> Hi,
> can anyone correct my understanding( if I am wrong) of the following
> function?
>
> This function should bring MIPS processor into debug mode .
> It sets bit 3 of  EJTAG_INST_CONTROL register.
>
>> int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
>> {
>>  uint32_t ejtag_ctrl;
>
> The command  causes that we will work with EJTAG_INST_CONTROL register(
> writes into instruction register)
>>  mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
>
>  set debug break bit . But what value must have ejtag_info->ejtag_ctrl ??
>>  ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;

Is it really important ?
What you want is to set up appropriate bit in the EJTAG_CTRL reg.

Grep more for this function. Who calls it ? That can be for example
mips_m4k_halt(). What is put in ejtag_ctrl ?
Is  ejtag_info global structure ? Who is affecting
ejtag_info->ejtag_ctrl during the program life until
mips_ejtag_enter_debug(), etc...

In the end, you will see that it is not really important and that
ejtag_info->ejtag_ctrl probably holds last value written or read
to/from EJTAG_CTRL register (as one should suppose just by reading the
names).

If you really really what to know what is inside, why do not you rung
OpenOCD in GDB, or just dump contents using good ol' printf ?

>
>
> write the debug break bit into data register
>>  mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
>>
> But what  will this command do??What value will ejtag_info->ejtag_ctrl have
> ?

Really not important. What is important is that you have set
appropriate bit into whatever value was before, and MIPS will
understand what you really wanted from it, and will gently pass to
DEBUG mode.

BR,
Drasko

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