Witht the KT-LINK design there is one signal (GPIOL1) that routes TDI and
TDO signal into SWDIOTMS pin, and one RnW (GPIOH4) signal that switches the
TDI output buffer for write, the TDO is always listening.
Therefore if you put a 1k resistor (or a diode with K at TDI) between TDI
and TDO and pull that high from a TDO with a 10k resistor there should be a
SWDIO at TDO line right..? When TDI is high the target can pull the bus low
(TDO is HiZ, target is the bus driver) and so there would be zeros and ones
flowing into TDO. When the TDI is low it will pull the bus low (TDO is HiZ
and target is HiZ), so the zeros and ones will flow out from the TDI...
Please try it out and let me know if/how it works :-)
Tomek
--
CeDeROM, SQ7MHZ, http://www.tomek.cedro.info
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