This is an automated email from Gerrit.

Hsiangkai Wang ([email protected]) just uploaded a new patch set to Gerrit, 
which you can find at http://openocd.zylin.com/1317

-- gerrit

commit 396555bd440136e54446b36db6166c05ca3138d0
Author: Hsiangkai <[email protected]>
Date:   Wed Mar 27 11:47:50 2013 +0800

    nds32: do not cache register values as writing registers
    
    There are some aliasing registers, for example, $sp and $ir16.
    If OpenOCD caches values as writing, there may be wrong updating
    before running.
    
    For example,
    write $sp with 0xffc0
    write $ir16 with 0xffc0
    write $sp with 0xffd0
    
    before running, OpenOCD will do
    write $sp with 0xffd0
    write $ir16 with 0xffc0
    
    However, we hope $sp to be 0xffd0, not 0xffc0.
    
    Change-Id: I5be6d74bfc724a25dd878691e742345aa1602c82
    Signed-off-by: Hsiangkai <[email protected]>

diff --git a/src/target/nds32.c b/src/target/nds32.c
index d948c82..c39d96e 100644
--- a/src/target/nds32.c
+++ b/src/target/nds32.c
@@ -190,24 +190,18 @@ static int nds32_set_core_reg(struct reg *reg, uint8_t 
*buf)
 
        buf_set_u32(reg->value, 0, 32, value);
 
-       /* update registers to take effect right now */
-       if ((MR6 == reg_arch_info->num) ||
-                       (MR7 == reg_arch_info->num)) {
-               LOG_DEBUG("writing register %i "
-                               "with value 0x%8.8" PRIx32, reg_arch_info->num, 
value);
-               aice->port->api->write_reg(reg_arch_info->num, 
reg_arch_info->value);
-               reg->valid = true;
-               reg->dirty = false;
+       LOG_DEBUG("writing register %i(%s) with value 0x%8.8" PRIx32,
+                       reg_arch_info->num, reg->name, value);
 
+       aice->port->api->write_reg(reg_arch_info->num, reg_arch_info->value);
+       reg->valid = true;
+       reg->dirty = false;
+
+       /* update registers to take effect right now */
+       if ((MR6 == reg_arch_info->num) || (MR7 == reg_arch_info->num)) {
                /* update lm information */
                nds32_update_lm_info(nds32);
        } else if (FUCPR == reg_arch_info->num) {
-               LOG_DEBUG("writing register %i "
-                               "with value 0x%8.8" PRIx32, reg_arch_info->num, 
value);
-               aice->port->api->write_reg(reg_arch_info->num, 
reg_arch_info->value);
-               reg->valid = true;
-               reg->dirty = false;
-
                /* update audio/fpu setting */
                if (value & 0x1)
                        nds32->fpu_enable = true;
@@ -218,9 +212,6 @@ static int nds32_set_core_reg(struct reg *reg, uint8_t *buf)
                        nds32->audio_enable = true;
                else
                        nds32->audio_enable = false;
-       } else {
-               reg->valid = true;
-               reg->dirty = true;
        }
 
        return ERROR_OK;

-- 

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