On 2013.07.02 08:08, Oleksij Rempel wrote: > enable debug mode and you will get some thing like "EJTAG: features ..."
Debug: 261 45327 mips_ejtag.c:352 mips_ejtag_init(): impcode: 0x00800904 Debug: 262 45327 mips_ejtag.c:359 mips_ejtag_init(): EJTAG: Version 1 or 2.0 Detected Debug: 263 45327 mips_ejtag.c:387 mips_ejtag_init(): EJTAG: features: R4k DMA MIPS32 Debug: 264 45328 mips_ejtag.c:390 mips_ejtag_init(): EJTAG: DMA Access Mode Support Enabled > you should try openocd with my changes: > https://github.com/olerem/openocd/commits/brake Oh, wow, **MUCH** better! -------------------------------------------------------------------- > bcm_halt Halting CPU... hardware datapoints: f, (ff30000) target state: halted target halted in MIPS32 mode due to debug-request, pc: 0x80434154 Disabling watchdog... -------------------------------------------------------------------- Registers (and pc) get nicely populated using your branch, and this looks more like proper halt state to me. Also, resume seems to work OK from what I could see. Great work! By the way, is there an option to specify libftdi 1.0 over 0.x? Right now I'm replacing the -lftdi with -lftdi1 in configure.ac & Makefile.am, but I'm wondering if I'm missing something in terms of conf. > i would really like to have some feedback from you. Very pleased with what I'm seeing so far. The mips cp0 commands do work this time around: > mips32 cp0 12 0 cp0 reg 12, select 0: 1000fc00 > mips32 cp0 15 0 cp0 reg 15, select 0: 00029010 > mips32 cp0 16 0 cp0 reg 16, select 0: 80008083 The doc I see for 4k and earlier seems to point to bit 15 of CP0 Register 16, Select 0 to indicate if the CPU is running in BE mode, so, from the above, it looks like mine is. Now the icing on the cake is that, after a slight modification of my base address (0x1fc00000 -> 0xbfc00000) my original config file is now able to probe the flash in (16 bit) CFI mode: -------------------------------------------------------------------- > flash probe 0 Flash Manufacturer/Device: 0x0001 0x227e Flash Manufacturer/Device: 0x0001 0x227e flash 'cfi' found at 0xbfc00000 > flash info 0 #0 : cfi at 0xbfc00000, size 0x00400000, buswidth 2, chipwidth 2 # 0: 0x00000000 (0x2000 8kB) not protected (...) # 70: 0x003f0000 (0x10000 64kB) not protected CFI flash: mfr: 0x0001, id:0x227e qry: 'QRY', pri_id: 0x0002, pri_addr: 0x0040, alt_id: 0x0000, alt_addr: 0x0000 Vcc min: 2.7, Vcc max: 3.6, Vpp min: 0.0, Vpp max: 0.0 typ. word write timeout: 128 us, typ. buf write timeout: 128 us, typ. block erase timeout: 1024 ms, typ. chip erase timeout: 1 ms max. word write timeout: 1024 us, max. buf write timeout: 4096 us, max. block erase timeout: 16384 ms, max. chip erase timeout: 1 ms size: 0x400000, interface desc: 2, max buffer write size: 0x20 Spansion primary algorithm extend information: pri: 'PRI', version: 1.3 Silicon Rev.: 0x2, Address Sensitive unlock: 0x0 Erase Suspend: 0x2, Sector Protect: 0x1 VppMin: 11.5, VppMax: 12.5 -------------------------------------------------------------------- Awesome!! :D Haven't tried to read or write anything yet, but I'll see if I can play further sometime this week. Really really nice. Can't wait for your changes to be integrated into mainline, as this should open the door to a much more Broadcom friendly OpenOCD. :) And once more, many thanks for the help there. If there's additional feedback you'd like to have, let me know - I'll see what I can do. Regards, /Pete ------------------------------------------------------------------------------ This SF.net email is sponsored by Windows: Build for Windows Store. http://p.sf.net/sfu/windows-dev2dev _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
