This is an automated email from Gerrit. Paul Fertser ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/1532
-- gerrit commit 0d9e76cc39ab29853be7b8fb9f69475292643eb9 Author: Paul Fertser <[email protected]> Date: Mon Jul 29 17:22:07 2013 +0400 [PoC] mdr32: preliminary support for Milandr's MDR32Fx This adds example config and preliminary flash driver for russian Cortex-M3 microcontroller model. Run-time tested on MDR32F9Q2I evaluation board; the flash driver should be compatible with MDR32F2x (Cortex-M0) too but I lack hardware to test. There're no status bits at all, the datasheets specifies some delays for flash operations instead. All being in <100us range, they're hard to violate with JTAG, I hope. There're also no flash identification registers so the flash size and type has to be hardcoded into the config. The flashing is considerably complicated because the flash is split into pages, and each page consists of 4 interleaved non-consecutive "sectors" (on MDR32F9 only, MDR32F2 is single-sectored), so the fastest way is to latch the page and sector address and then write only the part that should go into the current page and current sector. With adapter_khz 1000 the current code flashes all the 128k memory in 49.5s, the real performance should be reached when the target flash algorithm is written. Change-Id: I80c0632da686d49856fdbf9e05d908846dd44316 Signed-off-by: Paul Fertser <[email protected]> diff --git a/src/flash/nor/Makefile.am b/src/flash/nor/Makefile.am index 45a0c97..080b847 100644 --- a/src/flash/nor/Makefile.am +++ b/src/flash/nor/Makefile.am @@ -21,6 +21,7 @@ NOR_DRIVERS = \ lpc288x.c \ lpc2900.c \ lpcspifi.c \ + mdr.c \ non_cfi.c \ ocl.c \ pic32mx.c \ diff --git a/src/flash/nor/drivers.c b/src/flash/nor/drivers.c index 433d1c7..57ae15f 100644 --- a/src/flash/nor/drivers.c +++ b/src/flash/nor/drivers.c @@ -50,6 +50,7 @@ extern struct flash_driver dsp5680xx_flash; extern struct flash_driver fm3_flash; extern struct flash_driver kinetis_flash; extern struct flash_driver efm32_flash; +extern struct flash_driver mdr_flash; /** * The list of built-in flash drivers. @@ -84,6 +85,7 @@ static struct flash_driver *flash_drivers[] = { &dsp5680xx_flash, &kinetis_flash, &efm32_flash, + &mdr_flash, NULL, }; diff --git a/src/flash/nor/mdr.c b/src/flash/nor/mdr.c new file mode 100644 index 0000000..8fa0485 --- /dev/null +++ b/src/flash/nor/mdr.c @@ -0,0 +1,575 @@ +/*************************************************************************** + * Copyright (C) 2005 by Dominic Rath * + * [email protected] * + * * + * Copyright (C) 2008 by Spencer Oliver * + * [email protected] * + * * + * Copyright (C) 2011 by Andreas Fritiofson * + * [email protected] * + * * + * Copyright (C) 2013 by Paul Fertser * + * [email protected] * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * + ***************************************************************************/ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "imp.h" +#include <helper/binarybuffer.h> +#include <target/algorithm.h> +#include <target/armv7m.h> + +#define MD_RST_CLK 0x40020000 +#define MD_PER_CLOCK (MD_RST_CLK + 0x1C) +#define MD_PER_CLOCK_EEPROM (1 << 3) +#define MD_PER_CLOCK_RST_CLK (1 << 4) + +#define FLASH_REG_BASE 0x40018000 +#define FLASH_CMD (FLASH_REG_BASE + 0x00) +#define FLASH_ADR (FLASH_REG_BASE + 0x04) +#define FLASH_DI (FLASH_REG_BASE + 0x08) +#define FLASH_DO (FLASH_REG_BASE + 0x0C) +#define FLASH_KEY (FLASH_REG_BASE + 0x10) + +#define FLASH_NVSTR (1 << 13) +#define FLASH_PROG (1 << 12) +#define FLASH_MAS1 (1 << 11) +#define FLASH_ERASE (1 << 10) +#define FLASH_IFREN (1 << 9) +#define FLASH_SE (1 << 8) +#define FLASH_YE (1 << 7) +#define FLASH_XE (1 << 6) +#define FLASH_RD (1 << 2) +#define FLASH_WR (1 << 1) +#define FLASH_CON (1 << 0) +#define FLASH_DELAY_MASK (7 << 3) + +#define KEY 0x8AAA5551 + +struct mdr_flash_bank { + int probed; + size_t mem_type; + size_t page_count; + size_t sec_count; +}; + +/* flash bank <name> mdr <base> <size> 0 0 <target#> <type> <page_count> <sec_count> */ +FLASH_BANK_COMMAND_HANDLER(mdr_flash_bank_command) +{ + struct mdr_flash_bank *mdr_info; + + if (CMD_ARGC < 9) + return ERROR_COMMAND_SYNTAX_ERROR; + + mdr_info = malloc(sizeof(struct mdr_flash_bank)); + + bank->driver_priv = mdr_info; + mdr_info->probed = 0; + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[6], mdr_info->mem_type); + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[7], mdr_info->page_count); + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[8], mdr_info->sec_count); + return ERROR_OK; +} + +static int mdr_protect_check(struct flash_bank *bank) +{ + return ERROR_OK; +} + +static int mdr_mass_erase(struct flash_bank *bank) +{ + struct target *target = bank->target; + struct mdr_flash_bank *mdr_info = bank->driver_priv; + uint32_t flash_cmd; + int retval; + size_t i; + + retval = target_read_u32(target, FLASH_CMD, &flash_cmd); + if (retval != ERROR_OK) + return retval; + + for (i = 0; i < mdr_info->sec_count; i++) { + retval = target_write_u32(target, FLASH_ADR, i << 2); + if (retval != ERROR_OK) + return retval; + + flash_cmd |= FLASH_XE | FLASH_MAS1 | FLASH_ERASE; + retval = target_write_u32(target, FLASH_CMD, flash_cmd); + if (retval != ERROR_OK) + return retval; + flash_cmd |= FLASH_NVSTR; + retval = target_write_u32(target, FLASH_CMD, flash_cmd); + if (retval != ERROR_OK) + return retval; + flash_cmd &= ~FLASH_ERASE; + retval = target_write_u32(target, FLASH_CMD, flash_cmd); + if (retval != ERROR_OK) + return retval; + flash_cmd &= ~(FLASH_XE | FLASH_MAS1 | FLASH_NVSTR); + retval = target_write_u32(target, FLASH_CMD, flash_cmd); + if (retval != ERROR_OK) + return retval; + } + + return retval; +} + +static int mdr_erase(struct flash_bank *bank, int first, int last) +{ + struct target *target = bank->target; + struct mdr_flash_bank *mdr_info = bank->driver_priv; + int i, retval, retval2; + size_t j; + uint32_t flash_cmd, cur_per_clock; + + if (bank->target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + retval = target_read_u32(target, MD_PER_CLOCK, &cur_per_clock); + if (retval != ERROR_OK) + return retval; + + if (!(cur_per_clock & 0x10)) { + LOG_ERROR("Target needs reset before flash operations"); + return ERROR_FLASH_OPERATION_FAILED; + } + + retval = target_write_u32(target, MD_PER_CLOCK, cur_per_clock | MD_PER_CLOCK_EEPROM); + if (retval != ERROR_OK) + return retval; + + retval = target_write_u32(target, FLASH_KEY, KEY); + if (retval != ERROR_OK) + goto reset_pg_and_lock; + + retval = target_read_u32(target, FLASH_CMD, &flash_cmd); + if (retval != ERROR_OK) + goto reset_pg_and_lock; + + /* Switch on register access */ + flash_cmd = (flash_cmd & FLASH_DELAY_MASK) | FLASH_CON; + if (mdr_info->mem_type) + flash_cmd |= FLASH_IFREN; + retval = target_write_u32(target, FLASH_CMD, flash_cmd); + if (retval != ERROR_OK) + goto reset_pg_and_lock; + + if ((first == 0) && (last == (bank->num_sectors - 1))) { + retval = mdr_mass_erase(bank); + goto reset_pg_and_lock; + } + + size_t page_size = bank->size / mdr_info->page_count; + for (i = first; i <= last; i++) { + for (j = 0; j < mdr_info->sec_count; j++) { + retval = target_write_u32(target, FLASH_ADR, (i * page_size) | (j << 2)); + if (retval != ERROR_OK) + goto reset_pg_and_lock; + + flash_cmd |= FLASH_XE | FLASH_ERASE; + retval = target_write_u32(target, FLASH_CMD, flash_cmd); + if (retval != ERROR_OK) + goto reset_pg_and_lock; + flash_cmd |= FLASH_NVSTR; + retval = target_write_u32(target, FLASH_CMD, flash_cmd); + if (retval != ERROR_OK) + goto reset_pg_and_lock; + flash_cmd &= ~FLASH_ERASE; + retval = target_write_u32(target, FLASH_CMD, flash_cmd); + if (retval != ERROR_OK) + goto reset_pg_and_lock; + flash_cmd &= ~(FLASH_XE | FLASH_NVSTR); + retval = target_write_u32(target, FLASH_CMD, flash_cmd); + if (retval != ERROR_OK) + goto reset_pg_and_lock; + } + bank->sectors[i].is_erased = 1; + } + +reset_pg_and_lock: + flash_cmd &= FLASH_DELAY_MASK; + retval2 = target_write_u32(target, FLASH_CMD, flash_cmd); + if (retval == ERROR_OK) + retval = retval2; + + retval2 = target_write_u32(target, FLASH_KEY, 0); + if (retval == ERROR_OK) + retval = retval2; + + return retval; +} + +static int mdr_protect(struct flash_bank *bank, int set, int first, int last) +{ + return ERROR_OK; +} + +#if 0 +static int mdr_write_block(struct flash_bank *bank, uint8_t *buffer, + uint32_t offset, uint32_t count) +{ + struct stm32x_flash_bank *stm32x_info = bank->driver_priv; + struct target *target = bank->target; + uint32_t buffer_size = 16384; + struct working_area *write_algorithm; + struct working_area *source; + uint32_t address = bank->base + offset; + struct reg_param reg_params[5]; + struct armv7m_algorithm armv7m_info; + int retval = ERROR_OK; + + /* see contrib/loaders/flash/stm32f1x.S for src */ + + static const uint8_t stm32x_flash_write_code[] = { + /* #define STM32_FLASH_SR_OFFSET 0x0C */ + /* wait_fifo: */ + 0x16, 0x68, /* ldr r6, [r2, #0] */ + 0x00, 0x2e, /* cmp r6, #0 */ + 0x18, 0xd0, /* beq exit */ + 0x55, 0x68, /* ldr r5, [r2, #4] */ + 0xb5, 0x42, /* cmp r5, r6 */ + 0xf9, 0xd0, /* beq wait_fifo */ + 0x2e, 0x88, /* ldrh r6, [r5, #0] */ + 0x26, 0x80, /* strh r6, [r4, #0] */ + 0x02, 0x35, /* adds r5, #2 */ + 0x02, 0x34, /* adds r4, #2 */ + /* busy: */ + 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */ + 0x01, 0x27, /* movs r7, #1 */ + 0x3e, 0x42, /* tst r6, r7 */ + 0xfb, 0xd1, /* bne busy */ + 0x14, 0x27, /* movs r7, #0x14 */ + 0x3e, 0x42, /* tst r6, r7 */ + 0x08, 0xd1, /* bne error */ + 0x9d, 0x42, /* cmp r5, r3 */ + 0x01, 0xd3, /* bcc no_wrap */ + 0x15, 0x46, /* mov r5, r2 */ + 0x08, 0x35, /* adds r5, #8 */ + /* no_wrap: */ + 0x55, 0x60, /* str r5, [r2, #4] */ + 0x01, 0x39, /* subs r1, r1, #1 */ + 0x00, 0x29, /* cmp r1, #0 */ + 0x02, 0xd0, /* beq exit */ + 0xe5, 0xe7, /* b wait_fifo */ + /* error: */ + 0x00, 0x20, /* movs r0, #0 */ + 0x50, 0x60, /* str r0, [r2, #4] */ + /* exit: */ + 0x30, 0x46, /* mov r0, r6 */ + 0x00, 0xbe, /* bkpt #0 */ + }; + + /* flash write code */ + if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), + &write_algorithm) != ERROR_OK) { + LOG_WARNING("no working area available, can't do block memory writes"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + }; + + retval = target_write_buffer(target, write_algorithm->address, + sizeof(stm32x_flash_write_code), (uint8_t *)stm32x_flash_write_code); + if (retval != ERROR_OK) + return retval; + + /* memory buffer */ + while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) { + buffer_size /= 2; + buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */ + if (buffer_size <= 256) { + /* we already allocated the writing code, but failed to get a + * buffer, free the algorithm */ + target_free_working_area(target, write_algorithm); + + LOG_WARNING("no large enough working area available, can't do block memory writes"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + }; + + init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */ + init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */ + init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* buffer start */ + init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* buffer end */ + init_reg_param(®_params[4], "r4", 32, PARAM_IN_OUT); /* target address */ + + buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base); + buf_set_u32(reg_params[1].value, 0, 32, count); + buf_set_u32(reg_params[2].value, 0, 32, source->address); + buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size); + buf_set_u32(reg_params[4].value, 0, 32, address); + + armv7m_info.common_magic = ARMV7M_COMMON_MAGIC; + armv7m_info.core_mode = ARM_MODE_THREAD; + + retval = target_run_flash_async_algorithm(target, buffer, count, 2, + 0, NULL, + 5, reg_params, + source->address, source->size, + write_algorithm->address, 0, + &armv7m_info); + + if (retval == ERROR_FLASH_OPERATION_FAILED) { + LOG_ERROR("flash write failed at address 0x%"PRIx32, + buf_get_u32(reg_params[4].value, 0, 32)); + + if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) { + LOG_ERROR("flash memory not erased before writing"); + /* Clear but report errors */ + target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR); + } + + if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) { + LOG_ERROR("flash memory write protected"); + /* Clear but report errors */ + target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR); + } + } + + target_free_working_area(target, source); + target_free_working_area(target, write_algorithm); + + destroy_reg_param(®_params[0]); + destroy_reg_param(®_params[1]); + destroy_reg_param(®_params[2]); + destroy_reg_param(®_params[3]); + destroy_reg_param(®_params[4]); + + return retval; +} +#endif + +static int mdr_write(struct flash_bank *bank, uint8_t *buffer, + uint32_t offset, uint32_t count) +{ + struct target *target = bank->target; + struct mdr_flash_bank *mdr_info = bank->driver_priv; + uint8_t *new_buffer = NULL; + + if (bank->target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + if (offset & 0x3) { + LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte alignment", offset); + return ERROR_FLASH_DST_BREAKS_ALIGNMENT; + } + + /* If there's an odd number of bytes, the data has to be padded. Duplicate + * the buffer and use the normal code path with a single block write since + * it's probably cheaper than to special case the last odd write using + * discrete accesses. */ + int rem = count % 4; + if (rem) { + new_buffer = malloc(count + rem); + if (new_buffer == NULL) { + LOG_ERROR("odd number of bytes to write and no memory for padding buffer"); + return ERROR_FAIL; + } + LOG_INFO("odd number of bytes to write, padding with 0xff"); + buffer = memcpy(new_buffer, buffer, count); + while (rem--) + buffer[count++] = 0xff; + } + + uint32_t flash_cmd, cur_per_clock; + int retval, retval2; + + retval = target_read_u32(target, MD_PER_CLOCK, &cur_per_clock); + if (retval != ERROR_OK) + return retval; + + if (!(cur_per_clock & MD_PER_CLOCK_RST_CLK)) { + /* Something's very wrong if the RST_CLK module is not clocked */ + LOG_ERROR("Target needs reset before flash operations"); + return ERROR_FLASH_OPERATION_FAILED; + } + + retval = target_write_u32(target, MD_PER_CLOCK, cur_per_clock | MD_PER_CLOCK_EEPROM); + if (retval != ERROR_OK) + return retval; + + retval = target_write_u32(target, FLASH_KEY, KEY); + if (retval != ERROR_OK) + goto reset_pg_and_lock; + + retval = target_read_u32(target, FLASH_CMD, &flash_cmd); + if (retval != ERROR_OK) + goto reset_pg_and_lock; + + /* Switch on register access */ + flash_cmd = (flash_cmd & FLASH_DELAY_MASK) | FLASH_CON; + if (mdr_info->mem_type) + flash_cmd |= FLASH_IFREN; + retval = target_write_u32(target, FLASH_CMD, flash_cmd); + if (retval != ERROR_OK) + goto reset_pg_and_lock; + + /* try using a block write */ + /*retval = stm32x_write_block(bank, buffer, offset, words_remaining);*/ + retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + + if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) { + /* if block write failed (no sufficient working area), + * we use normal (slow) single halfword accesses */ + LOG_WARNING("Can't use block writes, falling back to single memory accesses"); + + size_t page_size = bank->size / mdr_info->page_count; + size_t page_mask = page_size - 1; + while (count > 0) { + size_t i, j; + size_t cur_page = offset & ~page_mask; + size_t bytes_to_write = cur_page + page_size - offset; + if (count < bytes_to_write) + bytes_to_write = count; + + /*LOG_INFO("Selecting next page: %08x", cur_page);*/ + + for (i = 0; i < mdr_info->sec_count; i++) { + retval = target_write_u32(target, FLASH_ADR, offset + i*4); + if (retval != ERROR_OK) + goto reset_pg_and_lock; + /*LOG_INFO("Selecting page/sector: %08x", offset + i*4);*/ + + flash_cmd |= FLASH_XE | FLASH_PROG; + retval = target_write_u32(target, FLASH_CMD, flash_cmd); + if (retval != ERROR_OK) + goto reset_pg_and_lock; + + flash_cmd |= FLASH_NVSTR; + retval = target_write_u32(target, FLASH_CMD, flash_cmd); + if (retval != ERROR_OK) + goto reset_pg_and_lock; + + for (j = 0; + (((offset + j + i*4) & ~page_mask) == cur_page) && + (j + i*4 < count); + j += mdr_info->sec_count*4) { + uint32_t value; + memcpy(&value, buffer + j + i*4, sizeof(uint32_t)); + retval = target_write_u32(target, FLASH_DI, value); + if (retval != ERROR_OK) + goto reset_pg_and_lock; + /*LOG_INFO("Writing to addr %08x", offset + j + i*4);*/ + retval = target_write_u32(target, FLASH_ADR, offset + j + i*4); + if (retval != ERROR_OK) + goto reset_pg_and_lock; + + flash_cmd |= FLASH_YE; + retval = target_write_u32(target, FLASH_CMD, flash_cmd); + if (retval != ERROR_OK) + goto reset_pg_and_lock; + flash_cmd &= ~FLASH_YE; + retval = target_write_u32(target, FLASH_CMD, flash_cmd); + if (retval != ERROR_OK) + goto reset_pg_and_lock; + } + flash_cmd &= ~FLASH_NVSTR; + retval = target_write_u32(target, FLASH_CMD, flash_cmd); + if (retval != ERROR_OK) + goto reset_pg_and_lock; + + flash_cmd &= ~(FLASH_XE | FLASH_PROG); + retval = target_write_u32(target, FLASH_CMD, flash_cmd); + if (retval != ERROR_OK) + goto reset_pg_and_lock; + } + + buffer += bytes_to_write; + offset += bytes_to_write; + count -= bytes_to_write; + } + } + +reset_pg_and_lock: + flash_cmd &= FLASH_DELAY_MASK; + retval2 = target_write_u32(target, FLASH_CMD, flash_cmd); + if (retval == ERROR_OK) + retval = retval2; + + retval2 = target_write_u32(target, FLASH_KEY, 0); + if (retval == ERROR_OK) + retval = retval2; + + if (new_buffer) + free(new_buffer); + + return retval; +} + +static int mdr_probe(struct flash_bank *bank) +{ + struct mdr_flash_bank *mdr_info = bank->driver_priv; + size_t page_count, page_size, i; + + if (bank->target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + page_count = mdr_info->page_count; + page_size = bank->size / page_count; + + bank->num_sectors = page_count; + bank->sectors = malloc(sizeof(struct flash_sector) * page_count); + + for (i = 0; i < page_count; i++) { + bank->sectors[i].offset = i * page_size; + bank->sectors[i].size = page_size; + bank->sectors[i].is_erased = -1; + bank->sectors[i].is_protected = 0; + } + + mdr_info->probed = 1; + + return ERROR_OK; +} + +static int mdr_auto_probe(struct flash_bank *bank) +{ + struct mdr_flash_bank *mdr_info = bank->driver_priv; + if (mdr_info->probed) + return ERROR_OK; + return mdr_probe(bank); +} + +static int get_mdr_info(struct flash_bank *bank, char *buf, int buf_size) +{ + struct mdr_flash_bank *mdr_info = bank->driver_priv; + snprintf(buf, buf_size, "MDR32Fx - %s", + mdr_info->mem_type ? "info memory" : "main memory"); + + return ERROR_OK; +} + +struct flash_driver mdr_flash = { + .name = "mdr", + .flash_bank_command = mdr_flash_bank_command, + .erase = mdr_erase, + .protect = mdr_protect, + .write = mdr_write, + .read = default_flash_read, + .probe = mdr_probe, + .auto_probe = mdr_auto_probe, + .erase_check = default_flash_blank_check, + .protect_check = mdr_protect_check, + .info = get_mdr_info, +}; diff --git a/tcl/target/mdr32f9q2i.cfg b/tcl/target/mdr32f9q2i.cfg new file mode 100644 index 0000000..a458ff7 --- /dev/null +++ b/tcl/target/mdr32f9q2i.cfg @@ -0,0 +1,48 @@ +# MDR32F9Q2I (1986ВЕ92У) +# http://milandr.ru/index.php?mact=Products,cntnt01,details,0&cntnt01productid=57&cntnt01returnid=68 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME mdr32f9q2i +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x8000 +} + +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz +adapter_khz 1000 + +adapter_nsrst_delay 100 +jtag_ntrst_delay 100 + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x4ba00477 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +flash bank $_CHIPNAME.flash mdr 0x08000000 0x20000 0 0 $_TARGETNAME 0 32 4 +# can't handle overlapping memory regions +# flash bank ${_CHIPNAME}_info.flash mdr 0x08000000 0x01000 0 0 $_TARGETNAME 1 1 4 + +# if srst is not fitted use SYSRESETREQ to +# perform a soft reset +cortex_m reset_config sysresetreq -- ------------------------------------------------------------------------------ See everything from the browser to the database with AppDynamics Get end-to-end visibility with application monitoring from AppDynamics Isolate bottlenecks and diagnose root cause in seconds. Start your free trial of AppDynamics Pro today! http://pubads.g.doubleclick.net/gampad/clk?id=48808831&iu=/4140/ostg.clktrk _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
