This is an automated email from Gerrit. Paul Fertser ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/2702
-- gerrit commit 0fab23e85f6af42f2dc96a25e4fad9287813e429 Author: Paul Fertser <[email protected]> Date: Thu Apr 9 15:20:22 2015 +0300 tcl/target/stm32f3: fix reset init for stlink Since stlink is not capable of half-word access, mwh shouldn't be used in the config ever. Change-Id: I9a4c1e58f002a1e5e99be1bd34aac27ba65d111d Reported-by: Uwe Bonnes <[email protected]> Signed-off-by: Paul Fertser <[email protected]> diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg index f3c22af..b6dd56b 100644 --- a/tcl/target/stm32f3x.cfg +++ b/tcl/target/stm32f3x.cfg @@ -105,7 +105,7 @@ proc stm32f3x_default_examine_end {} { proc stm32f3x_default_reset_init {} { # Configure PLL to boost clock to HSI x 8 (64 MHz) mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2] - mwh 0x40021002 0x0100 ;# RCC_CR[31:16] = PLLON + mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1] sleep 10 ;# Wait for PLL to lock mww 0x40021004 0x00380402 ;# RCC_CFGR |= SW[1] -- ------------------------------------------------------------------------------ BPM Camp - Free Virtual Workshop May 6th at 10am PDT/1PM EDT Develop your own process in accordance with the BPMN 2 standard Learn Process modeling best practices with Bonita BPM through live exercises http://www.bonitasoft.com/be-part-of-it/events/bpm-camp-virtual- event?utm_ source=Sourceforge_BPM_Camp_5_6_15&utm_medium=email&utm_campaign=VA_SF _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
