This is an automated email from Gerrit. Evan Hunter ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/2887
-- gerrit commit ce84eadd37a67bb89aba87fccbdfdda8d50bc7b2 Author: Broadcom WICED <[email protected]> Date: Tue Nov 18 15:29:33 2014 +0000 RTOS: Fix ThreadX support for Cortex-R4 There are actually two stacking types, indicated by the first word of the stack: 0 = Synchronous context switch stack type 1 = Interrupt stack type Change-Id: I47babe67f0ad972b6628aa0f6eefc8ef3eea7422 Signed-off-by: Evan Hunter <[email protected]> diff --git a/src/rtos/ThreadX.c b/src/rtos/ThreadX.c index fb9f5f7..be409d9 100644 --- a/src/rtos/ThreadX.c +++ b/src/rtos/ThreadX.c @@ -36,6 +36,7 @@ static int ThreadX_create(struct target *target); static int ThreadX_update_threads(struct rtos *rtos); static int ThreadX_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, char **hex_reg_list); static int ThreadX_get_symbol_list_to_lookup(symbol_table_elem_t *symbol_list[]); +static int threadx_r4_stack_read(struct target *target, int64_t stack_ptr, char **hex_reg_list); struct ThreadX_thread_state { int value; @@ -69,17 +70,19 @@ struct ThreadX_params { unsigned char thread_state_offset; unsigned char thread_next_offset; const struct rtos_register_stacking *stacking_info; + int (*threadx_special_stack_read)(struct target *target, int64_t stack_ptr, char **hex_reg_list); }; static const struct ThreadX_params ThreadX_params_list[] = { { - "cortex_m", /* target_name */ + "cortex_m", /* target_name */ 4, /* pointer_width; */ 8, /* thread_stack_offset; */ 40, /* thread_name_offset; */ 48, /* thread_state_offset; */ 136, /* thread_next_offset */ &rtos_standard_Cortex_M3_stacking, /* stacking_info */ + NULL, /* threadx_special_stack_read */ }, { "cortex_r4", /* target_name */ @@ -88,7 +91,8 @@ static const struct ThreadX_params ThreadX_params_list[] = { 40, /* thread_name_offset; */ 48, /* thread_state_offset; */ 136, /* thread_next_offset */ - &rtos_standard_Cortex_R4_stacking, /* stacking_info */ + NULL, /* stacking_info */ + threadx_r4_stack_read, /* threadx_special_stack_read */ }, }; @@ -324,7 +328,12 @@ static int ThreadX_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, cha return retval; } - return rtos_generic_stack_read(rtos->target, param->stacking_info, stack_ptr, hex_reg_list); + if (param->stacking_info != NULL) + return rtos_generic_stack_read(rtos->target, param->stacking_info, stack_ptr, hex_reg_list); + else if (param->threadx_special_stack_read != NULL) + return param->threadx_special_stack_read(rtos->target, stack_ptr, hex_reg_list); + + return -1; } static int ThreadX_get_symbol_list_to_lookup(symbol_table_elem_t *symbol_list[]) @@ -464,3 +473,82 @@ static int ThreadX_create(struct target *target) target->rtos->thread_details = NULL; return 0; } + +static const struct stack_register_offset threadx_Cortex_R4_stack_type0_offsets[] = { + { -1, 32 }, /* r0 (a1) */ + { -1, 32 }, /* r1 (a2) */ + { -1, 32 }, /* r2 (a3) */ + { -1, 32 }, /* r3 (a4) */ + { 0x08, 32 }, /* r4 (v1) */ + { 0x0c, 32 }, /* r5 (v2) */ + { 0x10, 32 }, /* r6 (v3) */ + { 0x14, 32 }, /* r7 (v4) */ + { 0x18, 32 }, /* r8 (a1) */ + { 0x1c, 32 }, /* r9 (sb) */ + { 0x20, 32 }, /* r10 (sl) */ + { 0x24, 32 }, /* r11 (fp) */ + { -1, 32 }, /* r12 (ip) */ + { -2, 32 }, /* sp */ + { 0x28, 32 }, /* lr */ + { 0x28, 32 }, /* pc */ + { 0x04, 32 }, /* CSPR */ +}; + + + +static const struct stack_register_offset threadx_Cortex_R4_stack_type1_offsets[] = { + { 0x08, 32 }, /* r0 (a1) */ + { 0x0c, 32 }, /* r1 (a2) */ + { 0x10, 32 }, /* r2 (a3) */ + { 0x14, 32 }, /* r3 (a4) */ + { 0x18, 32 }, /* r4 (v1) */ + { 0x1c, 32 }, /* r5 (v2) */ + { 0x20, 32 }, /* r6 (v3) */ + { 0x24, 32 }, /* r7 (v4) */ + { 0x28, 32 }, /* r8 (a1) */ + { 0x2c, 32 }, /* r9 (sb) */ + { 0x30, 32 }, /* r10 (sl) */ + { 0x34, 32 }, /* r11 (fp) */ + { 0x38, 32 }, /* r12 (ip) */ + { -2, 32 }, /* sp */ + { 0x3c, 32 }, /* lr */ + { 0x40, 32 }, /* pc */ + { 0x04, 32 }, /* SPSR */ +}; + +const struct rtos_register_stacking threadx_Cortex_R4_type0_stacking = { + 0x2C, /* stack_registers_size */ + -1, /* stack_growth_direction */ + 17, /* num_output_registers */ + 4, /* stack_alignment */ + threadx_Cortex_R4_stack_type0_offsets /* register_offsets */ +}; + +const struct rtos_register_stacking threadx_Cortex_R4_type1_stacking = { + 0x48, /* stack_registers_size */ + -1, /* stack_growth_direction */ + 17, /* num_output_registers */ + 4, /* stack_alignment */ + threadx_Cortex_R4_stack_type1_offsets /* register_offsets */ +}; + +static int threadx_r4_stack_read(struct target *target, int64_t stack_ptr, char **hex_reg_list) +{ + uint32_t stack_type; + int retval = target_read_buffer(target, (uint32_t)stack_ptr, 4, (uint8_t *) &stack_type); + if (retval != ERROR_OK) { + LOG_ERROR("Error reading stack type from thread"); + return retval; + } + + + LOG_DEBUG("ThreadX special R4 stack handling for type %d stack 0x%08x\n", stack_type, (unsigned int) stack_ptr); + if (stack_type == 0) { + retval = rtos_generic_stack_read(target, &threadx_Cortex_R4_type0_stacking, stack_ptr, hex_reg_list); + return retval; + } else if (stack_type == 1) + return rtos_generic_stack_read(target, &threadx_Cortex_R4_type1_stacking, stack_ptr, hex_reg_list); + + LOG_ERROR("ThreadX stack type unknown - is not 1 or 0"); + return -1; +} diff --git a/src/rtos/rtos_standard_stackings.c b/src/rtos/rtos_standard_stackings.c index 2eab86f..3268c1d 100644 --- a/src/rtos/rtos_standard_stackings.c +++ b/src/rtos/rtos_standard_stackings.c @@ -45,34 +45,7 @@ static const struct stack_register_offset rtos_standard_Cortex_M3_stack_offsets[ { 0x3c, 32 }, /* xPSR */ }; -static const struct stack_register_offset rtos_standard_Cortex_R4_stack_offsets[] = { - { 0x08, 32 }, /* r0 (a1) */ - { 0x0c, 32 }, /* r1 (a2) */ - { 0x10, 32 }, /* r2 (a3) */ - { 0x14, 32 }, /* r3 (a4) */ - { 0x18, 32 }, /* r4 (v1) */ - { 0x1c, 32 }, /* r5 (v2) */ - { 0x20, 32 }, /* r6 (v3) */ - { 0x24, 32 }, /* r7 (v4) */ - { 0x28, 32 }, /* r8 (a1) */ - { 0x2c, 32 }, /* r9 (sb) */ - { 0x30, 32 }, /* r10 (sl) */ - { 0x34, 32 }, /* r11 (fp) */ - { 0x38, 32 }, /* r12 (ip) */ - { -2, 32 }, /* sp */ - { 0x3c, 32 }, /* lr */ - { 0x40, 32 }, /* pc */ - { -1, 96 }, /* FPA1 */ - { -1, 96 }, /* FPA2 */ - { -1, 96 }, /* FPA3 */ - { -1, 96 }, /* FPA4 */ - { -1, 96 }, /* FPA5 */ - { -1, 96 }, /* FPA6 */ - { -1, 96 }, /* FPA7 */ - { -1, 96 }, /* FPA8 */ - { -1, 32 }, /* FPS */ - { 0x04, 32 }, /* CSPR */ -}; + static const struct stack_register_offset rtos_standard_NDS32_N1068_stack_offsets[] = { { 0x88, 32 }, /* R0 */ @@ -121,13 +94,6 @@ const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking = { rtos_standard_Cortex_M3_stack_offsets /* register_offsets */ }; -const struct rtos_register_stacking rtos_standard_Cortex_R4_stacking = { - 0x48, /* stack_registers_size */ - -1, /* stack_growth_direction */ - 26, /* num_output_registers */ - 8, /* stack_alignment */ - rtos_standard_Cortex_R4_stack_offsets /* register_offsets */ -}; const struct rtos_register_stacking rtos_standard_NDS32_N1068_stacking = { 0x90, /* stack_registers_size */ -- ------------------------------------------------------------------------------ _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
