This is an automated email from Gerrit. Evan Hunter ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/2886
-- gerrit commit f3657aa78e0a5fadec01f8b0dfba28fc56801319 Author: Evan Hunter <[email protected]> Date: Wed Jul 22 14:51:00 2015 +0100 tcl : Add support for LPC18xx parts Change-Id: I9fcf3f691f57fb44f10b9aca8ee3a765480712f9 Signed-off-by: Evan Hunter <[email protected]> diff --git a/tcl/target/lpc18xx.cfg b/tcl/target/lpc18xx.cfg new file mode 100644 index 0000000..becb6b3 --- /dev/null +++ b/tcl/target/lpc18xx.cfg @@ -0,0 +1,8 @@ +# NXP LPC18xx Cortex-M3 with at least 104kB SRAM +set CHIPNAME lpc18xx +set CHIPSERIES lpc1800 +if { ![info exists WORKAREASIZE] } { + set WORKAREASIZE 0x8000 +} + +source [find target/lpc1xxx.cfg] diff --git a/tcl/target/lpc1xxx.cfg b/tcl/target/lpc1xxx.cfg index 226425d..7980c7c 100644 --- a/tcl/target/lpc1xxx.cfg +++ b/tcl/target/lpc1xxx.cfg @@ -14,6 +14,7 @@ # LPC11Uxx chips support only SWD transports. # LPC13xx chips support only SWD transports. # LPC17xx chips support both JTAG and SWD transports. +# LPC18xx chips support both JTAG and SWD transports. # LPC40xx chips support both JTAG and SWD transports. # Adapt based on what transport is active. source [find target/swj-dp.tcl] @@ -26,7 +27,7 @@ if { [info exists CHIPNAME] } { if { [info exists CHIPSERIES] } { # Validate chip series is supported - if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700" && $CHIPSERIES != "lpc4000" } { + if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700" && $CHIPSERIES != "lpc1800" && $CHIPSERIES != "lpc4000" } { error "Unsupported LPC1xxx chip series specified." } set _CHIPSERIES $CHIPSERIES @@ -49,6 +50,8 @@ if { [info exists CCLK] } { set _CCLK 12000 } elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } { set _CCLK 4000 + } elseif { $_CHIPSERIES == "lpc1800" } { + set _CCLK 96000 } } @@ -59,10 +62,10 @@ if { [info exists CPUTAPID] } { # LPC8xx/LPC11xx/LPC12xx use a Cortex M0/M0+ core, LPC13xx/LPC17xx use a Cortex M3 core,LPC40xx use a Cortex-M4F core. if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } { set _CPUTAPID 0x0bb11477 - } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } { + } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc1800" || $_CHIPSERIES == "lpc4000" } { if { [using_jtag] } { set _CPUTAPID 0x4ba00477 - } { + } else { set _CPUTAPID 0x2ba01477 } } @@ -84,6 +87,7 @@ target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME # The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) # The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) # The LPC17xx devices have 8/16/32/64kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) +# The LPC18xx devices have 32/96kB of SRAM in the ARMv7-M "Code" area (at 0x10000000) # The LPC40xx devices have 16/32/64kB of SRAM in the ARMv7-ME "Code" area (at 0x10000000) $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE @@ -92,16 +96,26 @@ $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE # The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000) # The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000) # The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000) +# The LPC18xx devies have 512/768/1024kB of flash memory (at 0x1A000000) # The LPC40xx devies have 64/128/256/512kB of flash memory (at 0x00000000) # # All are compatible with the "lpc1700" variant of the LPC2000 flash driver # (same cmd51 destination boundary alignment, and all three support 256 byte # transfers). # + # flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum] set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \ - auto $_CCLK calc_checksum + +if { $_CHIPSERIES == "lpc1800" } { + flash bank $_FLASHNAME lpc2000 0x1A000000 0 0 0 $_TARGETNAME \ + auto $_CCLK calc_checksum +} +else +{ + flash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \ + auto $_CCLK calc_checksum +} if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } { # Do not remap 0x0000-0x0200 to anything but the flash (i.e. select @@ -135,6 +149,8 @@ if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "l $_TARGETNAME configure -event reset-init { mww 0x400FC040 0x01 } +} elseif { $_CHIPSERIES == "lpc1800" } { + # No remap settings required for LPC18xx } # Run with *real slow* clock by default since the -- ------------------------------------------------------------------------------ _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
