Hi Joerg On 17.10.2015 9:49, Joerg Wunsch wrote: > As Tomas Vanek wrote: > >> You can try proposed changes >> http://openocd.zylin.com/2778 >> http://openocd.zylin.com/2606 >> >> Check if SRST is connected to RESETN and configure >> reset_config srst_only >> and you should be able regain debug control after >> reset halt > I just gave that a try, too (on a homemade SAMD20 board). > > Alas, I still have two issues: > > * When using the "program" (Tcl?) command, the target does not > automatically run afterwards, but needs a hardware reset. I do have > this on a SAM4, too, so it's perhaps unrelated. The command ends up > in > > program '"$1"' exit > > Do I perhaps need a "reset run" before the exit? program filename reset exit ? Program command issues reset init so MCU is left halted without an extra command to resume/reset run > * When pressing the reset button while debugging, OpenOCD cannot > catch up again. I tried the "[mon] reset halt", but it still > yields: Yes, this is a "feature" of DSU unit. See ref man 12.6.2 CPU Reset extension. With change set #2778 you can release reset by command at91samd dsu_reset_deassert or by any use of reset driven by SWD adapter. I'm aware that OpenOCD should detect this state during poll and release reset automatically but it would need changes in cortex_m code. > Open On-Chip Debugger 0.10.0-dev-00036-g48787e1 (2015-10-03-15:03) > Licensed under GNU GPL v2 > For bug reports, read > http://openocd.org/doc/doxygen/bugs.html > adapter speed: 500 kHz > srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst > Info : only one transport option; autoselect 'swd' > Warn : Interface already configured, ignoring > srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst > adapter speed: 400 kHz > cortex_m reset_config sysresetreq > Info : CMSIS-DAP: SWD Supported > Info : CMSIS-DAP: JTAG Supported > Info : CMSIS-DAP: Interface Initialised (SWD) > Info : CMSIS-DAP: FW Version = 01.16.0041 > Info : SWCLK/TCK = 1 SWDIO/TMS = 1 TDI = 1 TDO = 1 nTRST = 0 nRESET = 1 > Info : CMSIS-DAP: Interface ready > Info : clock speed 400 kHz > Info : SWD IDCODE 0x0bc11477 > Info : at91samd20j18.cpu: hardware has 4 breakpoints, 2 watchpoints > Info : accepting 'gdb' connection on tcp/3333 > Info : SAMD MCU: SAMD20J18A (256KB Flash, 32KB RAM) > undefined debug reason 7 - target needs reset > Warn : WARNING! The target is already running. All changes GDB did to > registers will be discarded! Waiting for target to halt. > Warn : target at91samd20j18.cpu is not halted > Polling target at91samd20j18.cpu failed, trying to reexamine > Examination failed, GDB will be halted. Polling again in 100ms > Polling target at91samd20j18.cpu failed, trying to reexamine > Examination failed, GDB will be halted. Polling again in 300ms > Polling target at91samd20j18.cpu failed, trying to reexamine > Examination failed, GDB will be halted. Polling again in 700ms > Polling target at91samd20j18.cpu failed, trying to reexamine > Examination failed, GDB will be halted. Polling again in 1500ms > Polling target at91samd20j18.cpu failed, trying to reexamine > Examination failed, GDB will be halted. Polling again in 3100ms > Polling target at91samd20j18.cpu failed, trying to reexamine > Examination failed, GDB will be halted. Polling again in 6300ms > Info : AP write error, reset will not halt > Error: DP initialisation failed > in procedure 'reset' > in procedure 'ocd_bouncer' > > > Polling target at91samd20j18.cpu failed, trying to reexamine > Examination failed, GDB will be halted. Polling again in 6300ms > >
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