This is an automated email from Gerrit. Alamy Liu ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/3304
-- gerrit commit 65960b49d4faf159715ea5b6cf95996f5647c816 Author: Alamy Liu <[email protected]> Date: Mon Oct 5 11:19:24 2015 -0700 arm_dpm: Remove arm_reg_current() function pointer structure Change-Id: I2dbc692a1fc136e429da8512a98855b0e474f3b1 Signed-off-by: Alamy Liu <[email protected]> diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 35e6304..5e93ac5 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -671,8 +671,6 @@ static int aarch64_dpm_setup(struct aarch64_common *a8, uint32_t debug) if (retval != ERROR_OK) return retval; - dpm->arm_reg_current = armv8_reg_current; - retval = arm_dpm_initialize(dpm); return retval; diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c index 319c7e3..764ddbc 100644 --- a/src/target/arm_dpm.c +++ b/src/target/arm_dpm.c @@ -319,13 +319,19 @@ static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum) return dpm_write_reg32(dpm, r, regnum); } -static int arm_dpm_read_current_registers_i(struct arm_dpm *dpm) +/** + * Read basic registers of the the current context: R0 to R15, and CPSR; + * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb). + * In normal operation this is called on entry to halting debug state, + * possibly after some other operations supporting restore of debug state + * or making sure the CPU is fully idle (drain write buffer, etc). + */ +int arm_dpm_read_current_registers(struct arm_dpm *dpm) { struct arm *arm = dpm->arm; - uint32_t cpsr, instr, core_regs; + uint32_t cpsr; int retval; struct reg *r; - enum arm_state core_state = arm->core_state; retval = dpm->prepare(dpm); if (retval != ERROR_OK) @@ -340,25 +346,82 @@ static int arm_dpm_read_current_registers_i(struct arm_dpm *dpm) } r->dirty = true; + retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRS(0, 0), &cpsr); + if (retval != ERROR_OK) + goto fail; + + /* update core mode and state, plus shadow mapping for R8..R14 */ + arm_set_cpsr(arm, cpsr); + + /* REVISIT we can probably avoid reading R1..R14, saving time... */ + for (unsigned i = 1; i < arm->core_cache->num_regs; i++) { + r = arm_reg_current(arm, i); + if (r->valid) + continue; + + retval = dpm_read_reg(dpm, r, i); + if (retval != ERROR_OK) + goto fail; + } + + /* NOTE: SPSR ignored (if it's even relevant). */ + + /* REVISIT the debugger can trigger various exceptions. See the + * ARMv7A architecture spec, section C5.7, for more info about + * what defenses are needed; v6 debug has the most issues. + */ + +fail: + /* (void) */ dpm->finish(dpm); + return retval; +} + +int arm_dpm_read_current_registers_64(struct arm_dpm *dpm) +{ + struct arm *arm = dpm->arm; +// uint32_t cpsr, instr; + int retval; + struct reg *r; +// enum arm_state core_state = arm->core_state; + + retval = dpm->prepare(dpm); + if (retval != ERROR_OK) + return retval; + + /* read X0 first (it's used for scratch), then CPSR */ + r = arm->core_cache->reg_list + 0; + if (!r->valid) { + retval = dpm_read_reg(dpm, r, 0); + if (retval != ERROR_OK) + goto fail; + } + r->dirty = true; + + LOG_DEBUG("Alamy: CPSR is AArch32 mode register, use PSTATE elements"); +#if 0 + /* Alamy: CPSR is AArch32 mode register. + In AArch64, use PSTATE elements to get processor state */ +LOG_DEBUG("is_aarch64 is %d. core_state is %d", is_aarch64(arm->target), core_state); if (core_state == ARM_STATE_AARCH64) - instr = 0xd53b4500; /* mrs x0, dspsr_el0 */ +// instr = 0xd53b4500; /* mrs x0, dspsr_el0 */ + instr = ARMV8_MRS_DSPSR(0); // Alamy: from Vichy's armv8_dpm.c else instr = ARMV4_5_MRS(0, 0); retval = dpm->instr_read_data_r0(dpm, instr, &cpsr); if (retval != ERROR_OK) goto fail; +LOG_DEBUG("instr64 = 0x%08x, CPSR = 0x%08x", instr, cpsr); /* update core mode and state, plus shadow mapping for R8..R14 */ arm_set_cpsr(arm, cpsr); if (core_state == ARM_STATE_AARCH64) /* arm_set_cpsr changes core_state, restore it for now */ arm->core_state = ARM_STATE_AARCH64; - - core_regs = arm->core_cache->num_regs; +#endif /* REVISIT we can probably avoid reading R1..R14, saving time... */ - for (unsigned i = 1; i < core_regs; i++) { - r = dpm->arm_reg_current(arm, i); + for (unsigned i = 1; i < arm->core_cache->num_regs; i++) { + r = armv8_reg_current(arm, i); if (r->valid) continue; @@ -379,23 +442,6 @@ fail: return retval; } -/** - * Read basic registers of the the current context: R0 to R15, and CPSR; - * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb). - * In normal operation this is called on entry to halting debug state, - * possibly after some other operations supporting restore of debug state - * or making sure the CPU is fully idle (drain write buffer, etc). - */ -int arm_dpm_read_current_registers(struct arm_dpm *dpm) -{ - return arm_dpm_read_current_registers_i(dpm); -} - -int arm_dpm_read_current_registers_64(struct arm_dpm *dpm) -{ - return arm_dpm_read_current_registers_i(dpm); -} - /* Avoid needless I/O ... leave breakpoints and watchpoints alone * unless they're removed, or need updating because of single-stepping * or running debugger code. @@ -1140,10 +1186,6 @@ int arm_dpm_setup(struct arm_dpm *dpm) TYPE_FUNC_SET(add_watchpoint, dpm_add_watchpoint, dpm_add_watchpoint); TYPE_FUNC_SET(remove_watchpoint, dpm_remove_watchpoint, dpm_remove_watchpoint); - - if (dpm->arm_reg_current == 0) - dpm->arm_reg_current = arm_reg_current; - /* FIXME add vector catch support */ if (arm->core_state == ARM_STATE_AARCH64) { diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h index 8268673..2f0ae05 100644 --- a/src/target/arm_dpm.h +++ b/src/target/arm_dpm.h @@ -105,9 +105,6 @@ struct arm_dpm { int (*instr_read_data_x0)(struct arm_dpm *, uint32_t opcode, uint64_t *data); - struct reg *(*arm_reg_current)(struct arm *arm, - unsigned regnum); - /* BREAKPOINT/WATCHPOINT SUPPORT */ /** -- ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. Signup Now! http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140 _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
