This is an automated email from Gerrit. Matthias Welwarsky ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/3990
-- gerrit commit 844fa9ef958348db8a53e58706da951eff144609 Author: Matthias Welwarsky <[email protected]> Date: Wed Feb 15 15:30:21 2017 +0100 aarch64: reset fixes Make sure all core register caches are invalidated on reset assert, make sure to re-init debug registers on deassert. Change-Id: I82350d04cc3eaae5e35245d13d6c1fb0a8d59807 Signed-off-by: Matthias Welwarsky <[email protected]> diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 65a5278..d14b54d 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -169,6 +169,13 @@ static int aarch64_init_debug_access(struct target *target) LOG_DEBUG(" "); + retval = mem_ap_write_atomic_u32(armv8->debug_ap, + armv8->debug_base + CPUV8_DBG_OSLAR, 0); + if (retval != ERROR_OK) { + LOG_DEBUG("Examine %s failed", "oslock"); + return retval; + } + /* Clear Sticky Power Down status Bit in PRSR to enable access to the registers in the Core Power Domain */ retval = mem_ap_read_atomic_u32(armv8->debug_ap, @@ -1256,8 +1263,10 @@ static int aarch64_assert_reset(struct target *target) } /* registers are now invalid */ - if (target_was_examined(target)) + if (target_was_examined(target)) { register_cache_invalidate(armv8->arm.core_cache); + register_cache_invalidate(armv8->arm.core_cache->next); + } target->state = TARGET_RESET; @@ -1290,7 +1299,7 @@ static int aarch64_deassert_reset(struct target *target) } } - return ERROR_OK; + return aarch64_init_debug_access(target); } static int aarch64_write_apb_ap_memory(struct target *target, -- ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, SlashDot.org! http://sdm.link/slashdot _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
