I'm finally looking at this again. :-)

SMP isn't quite the behavior I would like. Specifically, it would be nice
to halt/resume different cores independently, and hardware breakpoints are
also unique per core.

To recap the problem:
On RISC-V multiple core use the same JTAG TAP. These cores will all be
RISC-V, but otherwise can vary arbitrarily (eg. one can be 32-bit, another
can be 64-bit, and they may even have different views of RAM). Switching
between cores happens by performing a JTAG scan. (More advanced features
allow to select multiple cores at once to facilitate simultaneous
run/halt/step, but I don't expect OpenOCD to support that.)
How can I make this work with OpenOCD? We're playing with a hack by
exposing multiple cores as OS threads, but that's not quite right.

Tim

On Wed, May 25, 2016 at 2:42 PM, Tim Newsome <[email protected]> wrote:

> Thanks. That looks promising. I'll play with it for real once I have a
> target that has more than one core. I'm happy that this infrastructure
> exists.
>
> Tim
>
> On Wed, May 25, 2016 at 1:41 PM, Andreas Färber <[email protected]> wrote:
>
>> Am 25.05.2016 um 01:34 schrieb Tim Newsome:
>> > RISC-V supports accessing more than one core through a single JTAG TAP.
>> > Is there an existing example in OpenOCD of a target that does the same
>> > thing?
>>
>> http://openocd.org/doc/html/Config-File-Guidelines.html -> 6.3.4
>>
>> HTH,
>> Andreas
>>
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