Hi!
On Mon, Jun 19, 2017 at 7:50 PM, Tim Newsome <[email protected]> wrote:
> I'm finally looking at this again. :-)
>
> SMP isn't quite the behavior I would like. Specifically, it would be nice
> to halt/resume different cores independently, and hardware breakpoints are
> also unique per core.
>
> To recap the problem:
> On RISC-V multiple core use the same JTAG TAP. These cores will all be
> RISC-V, but otherwise can vary arbitrarily (eg. one can be 32-bit, another
> can be 64-bit, and they may even have different views of RAM).
>
That sounds more like a regular multi-target setup than one multi-core
target. This would normally be handled with one target defined per core,
one gdb server per core etc. They are all completely independent of each
other, separate breakpoints and everything.
Is there any reason you'd want to treat it as a single SMP target?
> Switching between cores happens by performing a JTAG scan.
>
Basically the same principle as ARM DAP I guess, so you'd need a layer
between the targets and the TAP. Just don't copy the DAP code straight
away, it suffers from some architectural flaws that are hard to fix at this
point.
(More advanced features allow to select multiple cores at once to
> facilitate simultaneous run/halt/step, but I don't expect OpenOCD to
> support that.)
> How can I make this work with OpenOCD? We're playing with a hack by
> exposing multiple cores as OS threads, but that's not quite right.
>
Neat, but imagine the mess if you'd want to run a real OS awareness on top
of that... :)
/Andreas
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