This is an automated email from Gerrit. Daniel Glöckner ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/4248
-- gerrit commit cf1ec1263ea81ebee20bbf4fafb9501a8ef2f6c1 Author: Daniel Glöckner <[email protected]> Date: Sun Oct 8 12:15:04 2017 +0200 mips32: invalidate XBurst BTB when synchronizing caches This is also done by the U-Boot code released by Ingenic when synchronizing caches. The BTBV bit does not need to be cached/restored. It is always read as 0. Change-Id: Iaef02c5e74b73d46df6455701b74302029ac5d46 Signed-off-by: Daniel Glöckner <[email protected]> diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c index e9433d1..1f73af6 100644 --- a/src/target/mips32_pracc.c +++ b/src/target/mips32_pracc.c @@ -720,6 +720,14 @@ static int mips32_pracc_synchronize_cache(struct mips_ejtag *ejtag_info, } } pracc_add(&ctx, 0, MIPS32_SYNC(ctx.isa)); + + if (ejtag_info->has_xburst_btb) { + pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 8, 16, 7)); /* move config7 to $8 */ + pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 8, 8, 2)); /* set BTBV to invalidate branch target buffer */ + pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 8, 16, 7)); /* store $8 in config7 */ + pracc_add_li32(&ctx, 8, ejtag_info->reg8, 0); /* restore $8 */ + } + pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */ pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 15, 31, 0)); /* restore $15 from DeSave*/ -- ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
