Understood. I missed that, sorry.
Bas Vermeulen
On Fri, Nov 24, 2017 at 9:25 PM, Christopher Head <[email protected]> wrote:
> On November 24, 2017 7:03:38 AM PST, Bas Vermeulen <[email protected]>
> wrote:
> >However, cortex_a_read_cpu_memory_slow() issues a number of LDR{BHW}'s
> >to
> >read data,
> >but never actually updates r0 to read from a new address.
>
> ARMV4_5_LDR[BHW]_IP macros generate “LDR[BHW] r1, [r0], #1”. So r0 is
> post-incremented by the load instruction.
> --
> Christopher Head
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