This is an automated email from Gerrit.
Oleksij Rempel (li...@rempel-privat.de) just uploaded a new patch set to
Gerrit, which you can find at http://openocd.zylin.com/4424
-- gerrit
commit 3d0e844a47dc4dab844813789f38545b6db97ffe
Author: Oleksij Rempel <li...@rempel-privat.de>
Date: Mon Feb 19 17:00:17 2018 +0100
tcl/board: add DPTechnics DPT-Board-v1
it is Atheros AR9331 based IoT dev board.
Change-Id: I6fc3cdea1bef49c53045018ff5acfec4d5610ba6
Signed-off-by: Oleksij Rempel <li...@rempel-privat.de>
diff --git a/tcl/board/dptechnics_dpt-board-v1.cfg
b/tcl/board/dptechnics_dpt-board-v1.cfg
new file mode 100644
index 0000000..de31c7c
--- /dev/null
+++ b/tcl/board/dptechnics_dpt-board-v1.cfg
@@ -0,0 +1,32 @@
+# Product page:
+# https://www.dptechnics.com/en/products/dpt-board-v1.html
+#
+# JTAG is a 5 pin array located close to main module in following order:
+# 1. JTAG TCK
+# 2. JTAG TDO
+# 3. JTAG TDI
+# 4. JTAG TMS
+# 5. GND The GND is located near letter G of word JTAG on board.
+#
+# Two RST pins are connected to:
+# 1. GND
+# 2. GPIO11 this pin is located near letter R of word RST.
+#
+# To enable EJTAG mode, GPIO11 (RST[1]) pin should be pulled up. For example
+# with 10K resistor connected to V3.3 pin.
+#
+# This board is powered from micro USB connector. No real reset pin or button,
for
+# example RESET_L is available.
+
+source [find target/atheros_ar9331.cfg]
+
+$_TARGETNAME configure -event reset-init {
+ ar9331_25mhz_pll_init
+ sleep 1
+ ar9331_ddr2_init
+}
+
+set ram_boot_address 0xa0000000
+$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
+
+flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0
--
------------------------------------------------------------------------------
Check out the vibrant tech community on one of the world's most
engaging tech sites, Slashdot.org! http://sdm.link/slashdot
_______________________________________________
OpenOCD-devel mailing list
OpenOCD-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/openocd-devel
