This is an automated email from Gerrit.
Oleksij Rempel (li...@rempel-privat.de) just uploaded a new patch set to
Gerrit, which you can find at http://openocd.zylin.com/4427
-- gerrit
commit d76909179be97bdbaa5c22a20eb370e5b02c8cfc
Author: Oleksij Rempel <li...@rempel-privat.de>
Date: Thu Feb 22 09:42:59 2018 +0100
tcl/target: add Allwinner V3s SoC support
Change-Id: I2459d2b137050985b7301047f9651951d72d9e9e
Signed-off-by: Oleksij Rempel <li...@rempel-privat.de>
diff --git a/tcl/target/allwinner_v3s.cfg b/tcl/target/allwinner_v3s.cfg
new file mode 100644
index 0000000..2011802
--- /dev/null
+++ b/tcl/target/allwinner_v3s.cfg
@@ -0,0 +1,70 @@
+# The V3s processor represents Allwinner’s latest achievement in video encoding
+# processors, which integrates a single ARM Cortex TM -A7 CPU that operates at
+# speed up to 1.2GHz with supporting numerous peripherals. The processor
+# targets the need of the growing Car Digital Video Record (DVR) and IP Camera
+# (IPC) Monitor System.
+# A 512Mbit DDR2 is highly integrated in the V3s, in addition the V3s has
+# optimized external memory interfaces to SPI NAND /Nor flash, SD/MMC.
+#
+# Notes:
+# - ARM Cortex TM -A7 MP1 Processor
+# - Thumb-2 Technology
+# - Support NEON Advanced SIMD(Single Instruction Multiple Data)instruction
+# for acceleration of media and signal processing functions
+# - Support Large Physical Address Extensions(LPAE)
+# - VFPv4 Floating Point Unit
+# - 32KB L1 Instruction cache and 32KB L1 Data cache
+# - 128KB L2 cache
+#
+# Pins related for debug and bootstrap:
+# JTAG
+# JTAG_TMS PF0, SDC0_D1
+# JTAG_TDI PF1, SDC0_D0
+# JTAG_TDO PF3, SDC0_CMD
+# JTAG_TCK PF5, SDC0_D2
+# UART
+# None of UART ports seems to be enabled by ROM.
+# UART0_TX PF2, SDC0_CLK Per default disabled
+# UART0_RX PF4, SDC0_D3 Per default disabled
+# UART1_TX PE21 Per default disabled
+# UART1_RX PE22 Per default disabled
+# UART2_TX PB0 Per default disabled
+# UART2_RX PB1 Per default disabled
+#
+# JTAG is enabled by default after power on on listed JTAG_* pins. So far the
+# boot sequence is:
+# Time Action
+# 0000ms Power ON
+# 0200ms JTAG enabled
+# 0220ms JTAG pins switched to SD mode
+#
+# The time frame of 20ms can be neot enough to init and halt the CPU. In this
+# case I would recommend to set: "adapter_khz 15000"
+# After this it is possible to enable JTAG mode again from boot loader or OS.
+# Following DAPs are available:
+# dap[0]->MEM-AP AHB
+# dap[1]->MEM-AP APB->CA7[0]
+#
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME v3s
+}
+
+if { [info exists DAP_TAPID] } {
+ set _DAP_TAPID $DAP_TAPID
+} else {
+ set _DAP_TAPID 0x5ba00477
+}
+
+# No NRST or SRST is present on the SoC. Boards may provide
+# some sort of Power cycle reset for complete board or SoC.
+reset_config none srst_pulls_trst
+
+jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
+ -expected-id $_DAP_TAPID
+
+# Add Cortex A7 core
+set _TARGETNAME $_CHIPNAME.cpu_a7
+target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
--
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