Hi Vladimir, Please take a look at this guideline to submit patches to OpenOCD:
http://openocd.org/doc-release/doxygen/patchguide.html BR, Alan On 6/26/18, Vladimir Neyelov via OpenOCD-devel <[email protected]> wrote: > Hi all, > > I try to use Open OCD with bus blaster on our ARMv8 based board. Sometimes > bootloader is corrupted on the flash and BOOT ROM loads corrupted > > bootloader to SRAM and try run. Bootloader enables MMU and D/I caches in > register SCTLR (System Control Register) and stuck. > > We attach Open OCD to our board and do this steps: > > (gdb) target remote IP_ADDR:3333 > > (gdb) mon aarch64 disable_mmu -> disable MMU and d-cache bits in SCTLR > > (gdb) load bootloader.elf -> load bootloader image to SRAM > > (gdb) continue > > I implemented “disable_mmu” command in Open OCD code for aarch64 target > because I didn’t find similar command in the Open OCD. > > And there is no read/write access to SCTLR register. Please see below > disable MMU patch. Could you please integrate it to your git or suggest > > another option for disable MMU for aarch64. > > Thanks, > > Vladimir > > > > diff --git a/src/target/aarch64.c b/src/target/aarch64.c > > index df1e49c2..df256d7b 100644 > > --- a/src/target/aarch64.c > > +++ b/src/target/aarch64.c > > @@ -184,6 +184,54 @@ static int aarch64_mmu_modify(struct target *target, > int enable) > > return retval; > > } > > +int aarch64_disable_mmu(struct target *target) > > +{ > > + struct aarch64_common *aarch64 = target_to_aarch64(target); > > + struct armv8_common *armv8 = &aarch64->armv8_common; > > + int retval = ERROR_OK; > > + uint32_t instr = 0; > > + > > + if (aarch64->system_control_reg_curr & 0x4U) { > > + /* data cache is active */ > > + aarch64->system_control_reg_curr &= ~0x4U; > > + } > > + if ((aarch64->system_control_reg_curr & 0x1U)) { > > + aarch64->system_control_reg_curr &= ~0x1U; > > + } > > + LOG_DEBUG("System Control Register %x\n", > aarch64->system_control_reg_curr); > > + > > + switch (armv8->arm.core_mode) { > > + case ARMV8_64_EL0T: > > + case ARMV8_64_EL1T: > > + case ARMV8_64_EL1H: > > + instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL1, 0); > > + break; > > + case ARMV8_64_EL2T: > > + case ARMV8_64_EL2H: > > + instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL2, 0); > > + break; > > + case ARMV8_64_EL3H: > > + case ARMV8_64_EL3T: > > + instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL3, 0); > > + break; > > + > > + case ARM_MODE_SVC: > > + case ARM_MODE_ABT: > > + case ARM_MODE_FIQ: > > + case ARM_MODE_IRQ: > > + instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0); > > + break; > > + > > + default: > > + LOG_DEBUG("unknown cpu state 0x%" PRIx32, > armv8->arm.core_mode); > > + break; > > + } > > + > > + retval = armv8->dpm.instr_write_data_r0(&armv8->dpm, instr, > > + > aarch64->system_control_reg_curr); > > + return retval; > > +} > > + > > /* > > * Basic debug access, very low level assumes state is saved > > */ > > @@ -2545,6 +2593,13 @@ COMMAND_HANDLER(aarch64_handle_smp_off_command) > > return ERROR_OK; > > } > > +COMMAND_HANDLER(aarch64_handle_disable_mmu_command) > > +{ > > + struct target *target = get_current_target(CMD_CTX); > > + return aarch64_disable_mmu(target); > > +} > > + > > + > > COMMAND_HANDLER(aarch64_handle_smp_on_command) > > { > > struct target *target = get_current_target(CMD_CTX); > > @@ -2727,6 +2782,8 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, > Jim_Obj * const *argv) > > return JIM_OK; > > } > > + > > + > > static const struct command_registration aarch64_exec_command_handlers[] = > { > > { > > .name = "cache_info", > > @@ -2776,6 +2833,13 @@ static const struct command_registration > aarch64_exec_command_handlers[] = { > > .help = "read coprocessor register", > > .usage = "cpnum op1 CRn CRm op2", > > }, > > + { > > + .name = "disable_mmu", > > + .handler = aarch64_handle_disable_mmu_command, > > + .mode = COMMAND_EXEC, > > + .help = "disable mmu and dcache in System > Control Register", > > + .usage = "", > > + }, > > > > COMMAND_REGISTRATION_DONE > ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
