On Wed, Sep 12, 2018 at 1:44 PM, Liviu Ionescu <[email protected]> wrote:
> > > > On 12 Sep 2018, at 23:11, Tim Newsome <[email protected]> wrote: > > > > I would like a review on these changes: > > http://openocd.zylin.com/#/c/4655/ : Clarify what exactly the RISC-V > code supports. > > http://openocd.zylin.com/#/c/4656/ : Add flash support for SiFive's > Freedom E platforms > > > > Please let me know if there's anything else I need to do. > > once these patches are merged, is RISC-V support fully functional for > HiFive1 & Arty? > Almost. The `-rtos riscv` hack is still not in, but otherwise it should work. Multi-core should work in multi-gdb mode. Tim
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