On Donnerstag, 13. September 2018 21:23:25 CEST Tim Newsome wrote: > On Wed, Sep 12, 2018 at 1:44 PM, Liviu Ionescu <[email protected]> wrote: > > > On 12 Sep 2018, at 23:11, Tim Newsome <[email protected]> wrote: > > > > > > I would like a review on these changes: > > > http://openocd.zylin.com/#/c/4655/ : Clarify what exactly the RISC-V > > > > code supports. > > > > > http://openocd.zylin.com/#/c/4656/ : Add flash support for SiFive's > > > > Freedom E platforms > > > > > Please let me know if there's anything else I need to do. > > > > once these patches are merged, is RISC-V support fully functional for > > HiFive1 & Arty? > > Almost. The `-rtos riscv` hack is still not in, but otherwise it should > work. Multi-core should work in multi-gdb mode.
Tim, please check if http://openocd.zylin.com/#/c/3999/ is a sufficient replacement for the rtos hack. I'm pretty sure it's practically the same and I prefer to merge this instead of an architecture-bound solution. > > Tim -- Mit freundlichen Grüßen/Best regards, Matthias Welwarsky Project Engineer SYSGO AG Office Mainz Am Pfaffenstein 14 / D-55270 Klein-Winternheim / Germany Phone: +49-6136-9948-0 / Fax: +49-6136-9948-10 VoIP: SIP:[email protected] E-mail: [email protected] / Web: http://www.sysgo.com _________________________________________________________________________________ Web: https://www.sysgo.com Blog: https://www.sysgo.com/blog Events: https://www.sysgo.com/events Newsletter: https://www.sysgo.com/newsletter _________________________________________________________________________________ Handelsregister/Commercial Registry: HRB Mainz 90 HRB 8066 Vorstand/Executive Board: Etienne Butery (CEO), Kai Sablotny (COO) Aufsichtsratsvorsitzender/Supervisory Board Chairman: Marc Darmon USt-Id-Nr./VAT-Id-No.: DE 149062328
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