Hi, Thank you for the fast response. let me post the details regarding the same
here for more clarity on the issue.
# **olimex-arm-usb-ocd-h.cfg**
interface ftdi
ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-OCD-H"
ftdi_vid_pid 0x15ba 0x002b
ftdi_layout_init 0x0908 0x0b1b
ftdi_layout_signal nTRST -data 0x0100
ftdi_layout_signal LED -data 0x0800
ftdi_tdo_sample_edge falling # line added by sandeep to sample tdo on falling
edge of tck
reset_config trst_only
adapter_khz 1000
transport select jtag
jtag newtap auto0 tap -irlen 4 -expected-id 0x4ba00477
jtag newtap auto1 tap -irlen 7 -expected-id 0x00000497
target create auto0.tap cortex_m -chain-position auto0.tap -ap-num 0
**Log obtained from executing (./src/openocd -f
tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg)**
Open On-Chip Debugger 0.10.0 (2018-07-12-16:21)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
ftdi samples TDO on falling edge of TCK
trst_only separate trst_push_pull
adapter speed: 1000 kHz
auto0.tap
Info : clock speed 1000 kHz
Info : JTAG tap: auto0.tap tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd.),
part: 0xba00, ver: 0x4)
Info : JTAG tap: auto1.tap tap/device found: 0x00000497 (mfg: 0x24b (A-DATA
Technology), part: 0x0000, ver: 0x0)
Error: JTAG-DP STICKY ERROR
Error: Failed to read memory at 0xe000ed00
Error: JTAG-DP STICKY ERROR
Polling target auto0.tap failed, trying to reexamine
***(continuing the same in loop)***
***using telnet to connect (telnet localhost 4444) and executing (dap info) we
get the ROM TABLE PRINTED***
AP ID register 0x24770002
Type is MEM-AP APB
MEM-AP BASE 0x80000003
Valid ROM table present
Component base address 0x80000000
Peripheral ID 0x0000080000
Designer is 0x080, <invalid>
Part is 0x0, Unrecognized
Component class is 0x1, ROM table
MEMTYPE system memory not present: dedicated debug bus
ROMTABLE[0x0] = 0x100003
Component base address 0x80100000
Peripheral ID 0x04000bb4c1
Designer is 0x4bb, ARM Ltd.
Part is 0x4c1, Unrecognized
Component class is 0x1, ROM table
MEMTYPE system memory present on bus
[L01] ROMTABLE[0x0] = 0x1ff003
Component base address 0x802ff000
Peripheral ID 0x04000bb4c0
Designer is 0x4bb, ARM Ltd.
Part is 0x4c0, Cortex-M0+ ROM (ROM Table)
Component class is 0x1, ROM table
MEMTYPE system memory present on bus
[L02] ROMTABLE[0x0] = 0xfff0f003
Component base address 0x8020e000
Peripheral ID 0x04000bb008
Designer is 0x4bb, ARM Ltd.
Part is 0x8, Cortex-M0 SCS (System Control Space)
Component class is 0xe, Generic IP component
[L02] ROMTABLE[0x4] = 0xfff02003
Component base address 0x80201000
Peripheral ID 0x04000bb00a
Designer is 0x4bb, ARM Ltd.
Part is 0xa, Cortex-M0 DWT (Data Watchpoint and Trace)
Component class is 0xe, Generic IP component
[L02] ROMTABLE[0x8] = 0xfff03003
Component base address 0x80202000
Peripheral ID 0x04000bb00b
Designer is 0x4bb, ARM Ltd.
Part is 0xb, Cortex-M0 BPU (Breakpoint Unit)
Component class is 0xe, Generic IP component
[L02] ROMTABLE[0xc] = 0x0
[L02] End of ROM table
[L01] ROMTABLE[0x4] = 0x1002
Component not present
[L01] ROMTABLE[0x8] = 0x2002
Component not present
[L01] ROMTABLE[0xc] = 0x10000002
Component not present
[L01] ROMTABLE[0x10] = 0x0
[L01] End of ROM table
ROMTABLE[0x4] = 0x300003
Component base address 0x80300000
Peripheral ID 0x04000bb4c1
Designer is 0x4bb, ARM Ltd.
Part is 0x4c1, Unrecognized
Component class is 0x1, ROM table
MEMTYPE system memory present on bus
[L01] ROMTABLE[0x0] = 0x1ff003
Component base address 0x804ff000
Peripheral ID 0x04000bb4c0
Designer is 0x4bb, ARM Ltd.
Part is 0x4c0, Cortex-M0+ ROM (ROM Table)
Component class is 0x1, ROM table
MEMTYPE system memory present on bus
[L02] ROMTABLE[0x0] = 0xfff0f003
Component base address 0x8040e000
Peripheral ID 0x04000bb008
Designer is 0x4bb, ARM Ltd.
Part is 0x8, Cortex-M0 SCS (System Control Space)
Component class is 0xe, Generic IP component
[L02] ROMTABLE[0x4] = 0xfff02003
Component base address 0x80401000
Peripheral ID 0x04000bb00a
Designer is 0x4bb, ARM Ltd.
Part is 0xa, Cortex-M0 DWT (Data Watchpoint and Trace)
Component class is 0xe, Generic IP component
[L02] ROMTABLE[0x8] = 0xfff03003
Component base address 0x80402000
Peripheral ID 0x04000bb00b
Designer is 0x4bb, ARM Ltd.
Part is 0xb, Cortex-M0 BPU (Breakpoint Unit)
Component class is 0xe, Generic IP component
[L02] ROMTABLE[0xc] = 0x0
[L02] End of ROM table
[L01] ROMTABLE[0x4] = 0x1002
Component not present
[L01] ROMTABLE[0x8] = 0x2002
Component not present
[L01] ROMTABLE[0xc] = 0x10000002
Component not present
[L01] ROMTABLE[0x10] = 0x0
[L01] End of ROM table
ROMTABLE[0x8] = 0x503003
Component base address 0x80503000
Start address 0x80501000
Peripheral ID 0x24000f2103
Designer is 0x4f2, Tensilica
Part is 0x103, Unrecognized
Component class is 0x9, CoreSight component
Type is 0x15, Debug Logic, Processor
ROMTABLE[0xc] = 0x603003
Component base address 0x80603000
Start address 0x80601000
Peripheral ID 0x24000f2103
Designer is 0x4f2, Tensilica
Part is 0x103, Unrecognized
Component class is 0x9, CoreSight component
Type is 0x15, Debug Logic, Processor
ROMTABLE[0x10] = 0x700003
Component base address 0x80700000
Peripheral ID 0x04000bb4b5
Designer is 0x4bb, ARM Ltd.
Part is 0x4b5, Unrecognized
Component class is 0x1, ROM table
MEMTYPE system memory not present: dedicated debug bus
[L01] ROMTABLE[0x0] = 0x10003
Component base address 0x80710000
Peripheral ID 0x04004bbc15
Designer is 0x4bb, ARM Ltd.
Part is 0xc15, Cortex-R5 Debug (Debug Unit)
Component class is 0x9, CoreSight component
Type is 0x15, Debug Logic, Processor
[L01] ROMTABLE[0x4] = 0x12003
Component base address 0x80712000
Peripheral ID 0x04004bbc15
Designer is 0x4bb, ARM Ltd.
Part is 0xc15, Cortex-R5 Debug (Debug Unit)
Component class is 0x9, CoreSight component
Type is 0x15, Debug Logic, Processor
[L01] ROMTABLE[0x8] = 0x18002
Component not present
[L01] ROMTABLE[0xc] = 0x19002
Component not present
[L01] ROMTABLE[0x10] = 0x1c003
Component base address 0x8071c000
Peripheral ID 0x04000bb931
Designer is 0x4bb, ARM Ltd.
Part is 0x931, Cortex-R5 ETM (Embedded Trace)
Component class is 0x9, CoreSight component
Type is 0x13, Trace Source, Processor
[L01] ROMTABLE[0x14] = 0x1d002
Component not present
[L01] ROMTABLE[0x18] = 0x0
[L01] End of ROM table
ROMTABLE[0x14] = 0x800003
Component base address 0x80800000
Peripheral ID 0x0000080000
Designer is 0x080, <invalid>
Part is 0x0, Unrecognized
Component class is 0xe, Generic IP component
ROMTABLE[0x18] = 0x0
End of ROM table
---
** [tickets:#194] Accessing CORTEX-M0+ via APB**
**Status:** new
**Milestone:** 0.9.0
**Created:** Fri Jul 13, 2018 05:25 AM UTC by SANDEEP BABU
**Last Updated:** Fri Jul 13, 2018 12:20 PM UTC
**Owner:** nobody
**Attachments:**
-
[2018-07-09.png](https://sourceforge.net/p/openocd/tickets/194/attachment/2018-07-09.png)
(7.7 kB; image/png)
Hi,
We are using custom SoC design where the CORTEX M0+ cores are connected to the
DAPLITE via APB2AHB Bridge. We are able to access ROM tables via APB but we are
unable to access M0+ via APB as the JTAG debuggers (we have an Olimex
ARM-USB-OCD-H) by default search for M0+ in AHB bus only. Kindly, advise any
technique or methods to connect to M0+ core via APB in the setup mentioned. The
JTAG architecture diagram is attached.
Regards
Sandeep Babu
Ignitarium Technologies Pvt Ltd.
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