This is an automated email from Gerrit. Tomas Vanek ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/4723
-- gerrit commit f08a616fd3417e02b555a4f378ba20e1422d8cdb Author: Tomas Vanek <[email protected]> Date: Tue Oct 16 19:54:18 2018 +0200 tcl/target: imx6.cfg modified for the new reset platform Change-Id: I40911ea9ecc631192c3fac64c6bc822906c9acb0 Signed-off-by: Tomas Vanek <[email protected]> diff --git a/tcl/target/imx6.cfg b/tcl/target/imx6.cfg index 5b59ecf..3e4de40 100644 --- a/tcl/target/imx6.cfg +++ b/tcl/target/imx6.cfg @@ -13,48 +13,88 @@ if { [info exists DAP_TAPID] } { set _DAP_TAPID 0x4ba00477 } -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \ +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 \ -expected-id $_DAP_TAPID # SDMA / no IDCODE -jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f +jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 # System JTAG Controller -if { [info exists SJC_TAPID] } { - set _SJC_TAPID $SJC_TAPID +set _SJC_TAPID_S 0x0191b01d +set _SJC_TAPID_SL 0x0891f01d +set _SJC_TAPID_DL 0x0191a01d +set _SJC_TAPID_D 0x0191e01d +set _SJC_TAPID_Q 0x0191c01d + +if { [info exists SJC_TAPID ] } { + set _SJC_TAPID SJC_TAPID } else { - set _SJC_TAPID 0x0191c01d + switch $_CHIPNAME { + imx6s { set _SJC_TAPID $_SJC_TAPID_S } + imx6sl { set _SJC_TAPID $_SJC_TAPID_SL } + imx6dl { set _SJC_TAPID $_SJC_TAPID_DL } + imx6d { set _SJC_TAPID $_SJC_TAPID_D } + imx6q { set _SJC_TAPID $_SJC_TAPID_Q } + default { set _SJC_TAPID $_SJC_TAPID_Q } + } } -set _SJC_TAPID2 0x2191c01d -set _SJC_TAPID3 0x2191e01d -set _SJC_TAPID4 0x1191c01d -jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \ - -expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2 \ - -expected-id $_SJC_TAPID3 -expected-id $_SJC_TAPID4 +jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 \ + -expected-id $_SJC_TAPID -ignore-version # GDB target: Cortex-A9, using DAP, configuring only one core -# Base addresses of cores: +# Base addresses of core debug interfaces: # core 0 - 0x82150000 # core 1 - 0x82152000 # core 2 - 0x82154000 # core 3 - 0x82156000 -set _TARGETNAME $_CHIPNAME.cpu.0 +set _TARGETNAME $_CHIPNAME.cpu dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \ - -coreid 0 -dbgbase 0x82150000 +target create $_TARGETNAME.0 cortex_a \ + -dap $_CHIPNAME.dap \ + -coreid 0 -dbgbase 0x82150000 + +if { [ info exists SMP ] } { + switch $SMP { + 2 { + target create $_TARGETNAME.1 cortex_a \ + -dap $_CHIPNAME.dap \ + -coreid 1 -dbgbase 0x82152000 + target smp $_TARGETNAME.1 $_TARGETNAME.0 + } + 4 { + target create $_TARGETNAME.1 cortex_a \ + -dap $_CHIPNAME.dap \ + -coreid 1 -dbgbase 0x82152000 \ + -defer-examine + target create $_TARGETNAME.2 cortex_a \ + -dap $_CHIPNAME.dap \ + -coreid 2 -dbgbase 0x82154000 \ + -defer-examine + target create $_TARGETNAME.3 cortex_a \ + -dap $_CHIPNAME.dap \ + -coreid 3 -dbgbase 0x82156000 \ + -defer-examine + target smp $_TARGETNAME.3 $_TARGETNAME.2 \ + $_TARGETNAME.1 $_TARGETNAME.0 + } + } +} # some TCK cycles are required to activate the DEBUG power domain jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100" -proc imx6_dbginit {target} { - # General Cortex-A8/A9 debug initialisation - cortex_a dbginit +if { [ info exists SMP ] } { set _cores $SMP } else { set _cores 1 } +for { set _core 0 } { $_core < $_cores } { incr _core 1 } { + set t $_TARGETNAME.$_core +# $t configure -event reset-assert-pre "imx6_reset_handler pre $t" +# $t configure -event reset-assert-post "imx6_reset_handler middle $t" +# $t configure -event reset-deassert-post "imx6_reset_handler post $t" + set_arp_reset_handler $t arp_reset_handler_dbg_cleared $_core + $t configure -event reset-halt "arp_reset_simple_halter $t" } -# Slow speed to be sure it will work -adapter_khz 1000 -$_TARGETNAME configure -event reset-start { adapter_khz 1000 } +# i.MX6 device has reset input POR. It resets also JTAG and debug circuitry. +# Using JTAG_TRST is optional and has no benefits over srst_only operation. +reset_config srst_pulls_trst srst_gates_jtag -$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME" -$_TARGETNAME configure -event gdb-attach { halt } -- _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
