This is an automated email from Gerrit. Peter Lawrence ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/4855
-- gerrit commit ddf96a363e828b0890694af6068c4ba06883e9b2 Author: Peter Lawrence <[email protected]> Date: Wed Jan 16 18:00:34 2019 -0600 tcl: Support for Analog Devices ADSP-SC58x / ADSP-SC584-EZBRD The original script was broken by changes to the Cortex-A code. The recent introduction of the mem_ap target provided a new mechanism to allow the script to be fixed. This also adds an example board script for the ADSP-SC584-EZBRD. Change-Id: I36bc1ac6b6c036539f4175f1e65223ba10a35355 Signed-off-by: Peter Lawrence <[email protected]> diff --git a/tcl/board/adsp-sc584-ezbrd.cfg b/tcl/board/adsp-sc584-ezbrd.cfg new file mode 100644 index 0000000..82ad2d5 --- /dev/null +++ b/tcl/board/adsp-sc584-ezbrd.cfg @@ -0,0 +1,26 @@ +# +# Analog Devices ADSP-SC584-EZBRD evaluation board +# +# evaluation boards by Analog Devices (and designs derived from them) use a non-standard 10-pin 0.05" ARM Cortex Debug Connector +# pin 9 (GND or GNDDetect) has been usurped with JTAG /TRST +# as a result, a standards-compliant debug pod will only force the processor's debug interface into reset, preventing usage +# so, a connector adapter must be employed on these boards to isolate or otherwise prevent /TRST from being asserted + +# Analog expects users to use their proprietary ICE-1000 / ICE-2000 with this board, but +# this is an ARM target (and subject to the qualification above) many ARM debug pods should be compatible + +source [find interface/cmsis-dap.cfg] + +# Analog's silicon supports SWD and JTAG, but their ICE is limited to JTAG +# SWD is chosen here, as: +# 1) SWD is more efficient +# 2) OpenOCD in JTAG mode assumes /TRST usage +# /TRST is not part of the "Cortex" 10-pin ARM connector (which is why Analog overloaded the pinout) + +transport select swd + +# chosen speed is 'safe' choice, but your adapter may be capable of much higher rates +adapter_khz 400 + +source [find target/adsp-sc58x.cfg] + diff --git a/tcl/target/adsp-sc58x.cfg b/tcl/target/adsp-sc58x.cfg index e2b6952..50e5854 100644 --- a/tcl/target/adsp-sc58x.cfg +++ b/tcl/target/adsp-sc58x.cfg @@ -5,7 +5,6 @@ # as a result, a standards-compliant debug pod will only force the processor's debug interface into reset, preventing usage # so, a connector adapter must be employed on these boards to isolate or otherwise prevent /TRST from being asserted -transport select swd source [find target/swj-dp.tcl] if { [info exists CHIPNAME] } { @@ -26,9 +25,11 @@ if { [info exists CPUTAPID] } { set _CPUTAPID 0x3BA02477 } -swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create ap0.mem mem_ap -dap $_CHIPNAME.dap -ap-num 0 + set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_a -endian $_ENDIAN -dap $_CHIPNAME.dap @@ -39,8 +40,7 @@ $_TARGETNAME configure -event examine-end { proc sc58x_enabledebug {target} { # Enable debugging functionality by setting relevant bits in the TAPC_DBGCTL register - # the "phys" option is critical; the OpenOCD Cortex-A target code prevents normal mww when the target is not halted - # however, it is not possible to halt the target unless these register bits have been set - $target mww phys 0x31131000 0xFFFF + # it is not possible to halt the target unless these register bits have been set + ap0.mem mww 0x31131000 0xFFFF } -- _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
