You can write your own transport mechanism. It is not the rocket science, I
did it for our debug probes.
On Thu, 17 Jan 2019, 00:36 Tim Smith via OpenOCD-devel <
[email protected] wrote:
> ------------------------------
>
> * [tickets:#220] <https://sourceforge.net/p/openocd/tickets/220/> Generic
> OpenOCD driver for logical IR/DR scans to use our custom pod*
>
> *Status:* new
> *Milestone:* 0.9.0
> *Created:* Thu Jan 17, 2019 12:35 AM UTC by Tim Smith
> *Last Updated:* Thu Jan 17, 2019 12:35 AM UTC
> *Owner:* OpenOCD-Gerrit
>
> Hi,
> We have a simple JTAG debugger that can already do abasic foundational
> IR/DR scans to an ARM tap in our system using our own proprietary hardware
> pod. However now we wanted to use OpenOCD to do run control on this ARM
> microcontroller. Is it possible to bolt OpenOCD at a logical IR/DR scan
> payload level instead of at the physical JTAG pin level, because we wanted
> to use our own hardware debug adapter?. In otherwords, Is there a adapter
> driver that exists for logical jtag scans, something very similar to XT-OCD
> in Xtensa explorer for Tensilica cores?.
> Thanks in advance,
> Tim
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---
** [tickets:#220] Generic OpenOCD driver for logical IR/DR scans to use our
custom pod**
**Status:** new
**Milestone:** 0.9.0
**Created:** Thu Jan 17, 2019 12:35 AM UTC by Tim Smith
**Last Updated:** Thu Jan 17, 2019 12:35 AM UTC
**Owner:** OpenOCD-Gerrit
Hi,
We have a simple JTAG debugger that can already do abasic foundational IR/DR
scans to an ARM tap in our system using our own proprietary hardware pod.
However now we wanted to use OpenOCD to do run control on this ARM
microcontroller. Is it possible to bolt OpenOCD at a logical IR/DR scan payload
level instead of at the physical JTAG pin level, because we wanted to use our
own hardware debug adapter?. In otherwords, Is there a adapter driver that
exists for logical jtag scans, something very similar to XT-OCD in Xtensa
explorer for Tensilica cores?.
Thanks in advance,
Tim
---
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