This is an automated email from Gerrit. Christopher Head ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/5028
-- gerrit commit 2e309cfad95a8ebd03337af11ba39b65dd312d11 Author: Christopher Head <[email protected]> Date: Mon Apr 1 16:02:09 2019 -0700 Fix incorrect commas in URLs In Texinfo, a comma inside an @url separates parameters to the @url function rather than being included as part of a parameter. Use @comma{} instead to resolve this. Change-Id: I8b38939462cf4452e5bc2582ee484220aaf83ae0 Signed-off-by: Christopher Head <[email protected]> diff --git a/doc/openocd.texi b/doc/openocd.texi index 027e6d2..e090617 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -4375,14 +4375,14 @@ The current implementation supports three JTAG TAP cores: @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs, allowing access to physical memory addresses independently of CPU cores. @itemize @minus -@item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag}) +@item @code{OpenCores TAP} (See: @url{http://opencores.org/project@comma{}jtag}) @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf}) @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf}) @end itemize And two debug interfaces cores: @itemize @minus -@item @code{Advanced debug interface} (See: @url{http://opencores.org/project,adv_debug_sys}) -@item @code{SoC Debug Interface} (See: @url{http://opencores.org/project,dbg_interface}) +@item @code{Advanced debug interface} (See: @url{http://opencores.org/project@comma{}adv_debug_sys}) +@item @code{SoC Debug Interface} (See: @url{http://opencores.org/project@comma{}dbg_interface}) @end itemize @end itemize @end deffn -- _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
