This is an automated email from Gerrit. Christopher Head ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/5188
-- gerrit commit e65d6f455da31e486ea176c48b85efb1432b76fb Author: Christopher Head <[email protected]> Date: Thu May 30 12:24:26 2019 -0700 target/stm32h7x: enable PLL in reset-init handler With no PLL and a 4 MHz JTAG clock, there are lots of DAP WAITs during a program and an overall rate of ~33 kiB/s. With a PLL bringing the system clock up to 200 MHz, a JTAG clock of 8 MHz can be used with no DAP WAITs, achieving a program rate of ~100 kiB/s. Change-Id: I5e9f0ad49ec0e16451b12129d3f761798da7f50f Signed-off-by: Christopher Head <[email protected]> diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg index 0bfc43d..968e846 100644 --- a/tcl/target/stm32h7x.cfg +++ b/tcl/target/stm32h7x.cfg @@ -107,7 +107,28 @@ $_TARGETNAME configure -event trace-config { } $_TARGETNAME configure -event reset-init { - # Clock after reset is HSI at 64 MHz, no need of PLL - adapter_khz 4000 + # The clock after reset is HSI at 64 MHz. A PLL is not needed for JTAG to + # work properly overall, but enabling it does eliminate DAP WAITs while + # programming. + # + # Configure PLL1 to divide the 64 MHz HSI by 32 giving 2, then multiply the + # 2 by 100 giving 200 MHz for the CPU. This is the fastest that we can run + # at without needing to muck around with voltage scaling. + + # RCC_PLLCFGR &= ~(DIVQ1EN | DIVR1EN | DIVP2EN | DIVQ2EN | DIVR2EN | DIVP3EN | DIVQ3EN | DIVR3EN) + mmw 0x5802442C 0 0x01FE0000 + # RCC_PLL1DIVR = DIVR1(0) | DIVQ1(0) | DIVP1(0) | DIVN1(99) + mww 0x58024430 99 + # RCC_CR |= PLL1ON + mmw 0x58024400 0x01000000 0 + # !(RCC_CR & PLL1RDY) + while {!([mrw 0x58024400] & 0x02000000)} {} + # RCC_CFGR |= SW_PLL1 + mmw 0x58024410 0x3 0 + # RCC_CFGR & SWS != PLL1 + while {([mrw 0x58024410] & 0x38) != 0x18} {} + + # We can now use a faster clock speed. + adapter_khz 8000 } -- _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
