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Florian Fainelli ([email protected]) just uploaded a new patch set to 
Gerrit, which you can find at http://openocd.zylin.com/5211

-- gerrit

commit fc16ef6d1e1a0a2f79ca52741e29a693a5d9fc1d
Author: Florian Fainelli <[email protected]>
Date:   Tue Mar 19 09:50:41 2019 -0700

    armv7a_mmu: Do not restrict virtual addresses to uint32_t
    
    In preparation for adding super section decoding, do not restrict
    armv7a_mmu_translate_va_pa() to 32-bit virtual addresses since ARMv7-A
    processors with VMSA extensions (including LPAE) can issue wider
    physical addresses. Update casting to uint32_t where necessary.
    
    Change-Id: Id1c3d0d5ac324cbdc334259d9ea75fe4981671a1
    Signed-off-by: Florian Fainelli <[email protected]>

diff --git a/src/target/armv7a_mmu.c b/src/target/armv7a_mmu.c
index 153bfcc..7af1137 100644
--- a/src/target/armv7a_mmu.c
+++ b/src/target/armv7a_mmu.c
@@ -122,7 +122,7 @@ int armv7a_mmu_translate_va(struct target *target,  
uint32_t va, uint32_t *val)
 
 /*  V7 method VA TO PA  */
 int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
-       uint32_t *val, int meminfo)
+       target_addr_t *val, int meminfo)
 {
        int retval = ERROR_FAIL;
        struct armv7a_common *armv7a = target_to_armv7a(target);
@@ -142,7 +142,7 @@ int armv7a_mmu_translate_va_pa(struct target *target, 
uint32_t va,
                goto done;
        retval = dpm->instr_read_data_r0(dpm,
                        ARMV4_5_MRC(15, 0, 0, 7, 4, 0),
-                       val);
+                       (uint32_t *)val);
        /* decode memory attribute */
        NOS = (*val >> 10) & 1; /*  Not Outer shareable */
        NS = (*val >> 9) & 1;   /* Non secure */
@@ -153,7 +153,7 @@ int armv7a_mmu_translate_va_pa(struct target *target, 
uint32_t va,
                goto done;
        *val = (*val & ~0xfff)  +  (va & 0xfff);
        if (meminfo) {
-               LOG_INFO("%" PRIx32 " : %" PRIx32 " %s outer shareable %s 
secured",
+               LOG_INFO("%" PRIx32 " : %" TARGET_PRIxADDR " %s outer shareable 
%s secured",
                        va, *val,
                        NOS == 1 ? "not" : " ",
                        NS == 1 ? "not" : "");
diff --git a/src/target/armv7a_mmu.h b/src/target/armv7a_mmu.h
index 4372aa8..9f16e2c 100644
--- a/src/target/armv7a_mmu.h
+++ b/src/target/armv7a_mmu.h
@@ -21,7 +21,7 @@
 
 extern int armv7a_mmu_translate_va(struct target *target,  uint32_t va, 
uint32_t *val);
 extern int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
-       uint32_t *val, int meminfo);
+       target_addr_t *val, int meminfo);
 
 extern const struct command_registration armv7a_mmu_command_handlers[];
 
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 9fc2652..158de0b 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -2922,7 +2922,7 @@ static int cortex_a_virt2phys(struct target *target,
        if (retval != ERROR_OK)
                return retval;
        return armv7a_mmu_translate_va_pa(target, (uint32_t)virt,
-                                                   (uint32_t *)phys, 1);
+                                                   phys, 1);
 }
 
 COMMAND_HANDLER(cortex_a_handle_cache_info_command)

-- 


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