Custom board (<60mVpp ripple), jumper wires, chinese clone of stlink. But wait!
When I let my code to configure clocks (using PLL to run on 24MHz) I can crank
up SWD frequency to 4MHz without problem.
I did a little testing and swd itself seems to run fine at 1800 kHz after
`reset init`.
Whenever I try to load hex file to flash, no matter what clk source and
frequency MCU uses, it fails on 950kHz and higher. (no more steps between 450
and 950 kHz avilable)
Power path layout is in attachment. I don't think its that bad. Lowest runtime
voltage (biggest spike drop) is to 3.15V. MCU is STM32L011 in TSSOP14 package.
Attachments:
-
[19-07-04_22-49-34.png](https://sourceforge.net/p/openocd/tickets/_discuss/thread/10886657f3/d91e/attachment/19-07-04_22-49-34.png)
(157.9 kB; image/png)
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** [tickets:#242] STM32L0x too high SWD clock**
**Status:** new
**Milestone:** 0.9.0
**Labels:** STM32
**Created:** Thu Jul 04, 2019 04:30 PM UTC by Patrik Bachan
**Last Updated:** Thu Jul 04, 2019 07:47 PM UTC
**Owner:** nobody
Hi,
when calling `reset init` on STM32L0x target, function `stm32l0_enable_HSI16`
is called which bumps SWD frequency to 2500kHz. My adapter (STlink-V2) rounds
it to 1800MHz, but it is still too high. Communication breaks and reset is
needed. Wiring might be problem, I am not sure. (F7 worked on 1800kHz
flawlessly with significantly longer wires)
My point is, that 2.5MHz is pretty high clock frequency to set it so blindly.
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