---
** [tickets:#261] NXP S32G custom DAP support question**
**Status:** new
**Milestone:** 0.9.0
**Created:** Tue Mar 03, 2020 07:45 PM UTC by Bill Paul
**Last Updated:** Tue Mar 03, 2020 07:45 PM UTC
**Owner:** nobody
NXP has recently released a new family of automotive processors called the
S32G. I had to do some development on a board with an S32G274A processor, which
includes four Cortex-A53 cores (2 clusters of 2 cores each) and three Cortex-M7
cores. I wanted to use my Olimex ARM-USB-OCD-H debugger and OpenOCD with it
(the reference board has a standard 20-pin ARM JTAG connector).
I managed to get it to work, but I have a question (and I figured I'd shared
what I did to make it function so that maybe S32G support could be added to
OpenOCD eventually).
The S32G274 is a little unusual in that it has a custom NXP JTAG Controller
(JTAGC) which, according to the documentation, works in parallel with the ARM
TAP controller (JTAG DP or ARM DAP). The standard ARM JTAG register interface
is defined here:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0316d/Chdhbbjd.html
As you can see, only 4 bits are used to specify which register to access
(IDCODE, DPACC, APACC, etc...). This corresponds with the options specified to
the "jtag newtap" command in the config file for a typical ARM processor, e.g.:
~~~
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0xf \
-expected-id $_DAP_TAPID
~~~
The custom JTAG controller in the S32G274 is a little different: it supports up
to 256 registers, and hence has an irlen of 8, not 4. It has its own custom
interface, but the standard ARM IR instructions are encoded at the end of this
register space. That is, instead of sending 4 bits, you have to send 8, with a
prefix of four 1 bits.
In order to get OpenOCD to work, you therefore have to change the irlen in the
config file from 4 to 8. That helps, but I could not find a way to get OpenOCD
to send also an extra 4-bit prefix using just the configu file alone. I had to
resort to editing the adi_v5_jtag.c source and make the following small change:
~~~
diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index c2100eb4..1d07e232 100644
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -43,10 +43,10 @@
/*#define DEBUG_WAIT*/
/* JTAG instructions/registers for JTAG-DP and SWJ-DP */
-#define JTAG_DP_ABORT 0x8
-#define JTAG_DP_DPACC 0xA
-#define JTAG_DP_APACC 0xB
-#define JTAG_DP_IDCODE 0xE
+#define JTAG_DP_ABORT 0xF8
+#define JTAG_DP_DPACC 0xFA
+#define JTAG_DP_APACC 0xFB
+#define JTAG_DP_IDCODE 0xFE
/* three-bit ACK values for DPACC and APACC reads */
#define JTAG_ACK_OK_FAULT 0x2
~~~
As you can see, all I did was change the 0x8, 0xA, 0xB and 0xE instructions
into 0xF8, 0xFA, 0xFB and 0xFE. I also changed the newtap command like this:
~~~
jtag newtap $_CHIPNAME sjc -irlen 8 -ircapture 0x01 -irmask 0xff \
-expected-id 0x0830101d
~~~
With these modifications I can connect to the ARM cores and debug just fine:
~~~
Open On-Chip Debugger 0.10.0+dev-01047-g09ac9ab1 (2020-02-04-13:05)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
DEPRECATED! use 'adapter speed' not 'adapter_khz'
DEPRECATED! use 'adapter srst delay' not 'adapter_nsrst_delay'
Error: Invalid command argument
trst_and_srst separate srst_gates_jtag trst_push_pull srst_push_pull
connect_deassert_srst
force hard breakpoints
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : clock speed 1000 kHz
Error: interface can't drive 'nSRST' high
Info : JTAG tap: s32g.sjc tap/device found: 0x0830101d (mfg: 0x00e (Freescale
(Motorola)), part: 0x8301, ver: 0x0)
Real IDCODE: 0x0BA03477
Info : s32g.a53.0: hardware has 6 breakpoints, 4 watchpoints
Info : Listening on port 3333 for gdb connections
Info : Listening on port 3334 for gdb connections
~~~
It also turns out that the source code change still allows OpenOCD to work with
other ARM targets where irlen is still 4 (the upper 4 bits are just never
sent). I confirmed this by testing with an NXP i.MX8M board, which does not
have the custom interface.
For reference, I also uploaded the scripts I used here:
https://people.freebsd.org/~wpaul/w00t/s32g/
Note that there are 7 different scripts: the first four are for the Cortex-A53
cores and the last three are for the Cortex-M7 cores.
My question is: is there a better way to go about this? As I said, I couldn't
find a way to make this work solely through config file changes, but I don't
have an exhaustive knowledge of the config file syntax so I could have missed
something. And while this source change doesn't seem to break backward
compatibility with other ARM JTAG configurations, it feels like a hack. I don't
know if there's supposed to be some standard way of dealing with this. NXP has
an S32 debug probe of its own, and the S32 line is also supported by
Lauterbach, but I don't know what they do to deal with this.
Note that this is not a bug report per se. I'm actually happy with how OpenOCD
works with the S32G now that I've made this small change. (It saved me a lot of
grief.)
-Bill
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