This is an automated email from Gerrit. Tarek BOCHKATI ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/5795
-- gerrit commit 0dde9921d8961699ae3aaf3b7991acb03df51f0e Author: Tarek BOCHKATI <[email protected]> Date: Tue Aug 11 10:44:51 2020 +0100 arm_disassembler: rename struct 'arm_b_bl_bx_blx_instr' to 'arm_branch_instr' armv8m cores with security extension provides two additional branch instructions: bxns and blxns. extending the struct name to arm_b_bl_bx_blx_bxns_blxns_instr is not an option, then just rename it to 'struct arm_branch_instr' for genericity. Change-Id: Ida5b1d3af0e8bb9c4160afb50c3ec4c87005f7ce Signed-off-by: Tarek BOCHKATI <[email protected]> diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c index 59c0537..5be4c46 100644 --- a/src/target/arm_disassembler.c +++ b/src/target/arm_disassembler.c @@ -336,8 +336,8 @@ static int evaluate_blx_imm(uint32_t opcode, opcode, target_address); - instruction->info.b_bl_bx_blx.reg_operand = -1; - instruction->info.b_bl_bx_blx.target_address = target_address; + instruction->info.branch.reg_operand = -1; + instruction->info.branch.target_address = target_address; return ERROR_OK; } @@ -378,8 +378,8 @@ static int evaluate_b_bl(uint32_t opcode, COND(opcode), target_address); - instruction->info.b_bl_bx_blx.reg_operand = -1; - instruction->info.b_bl_bx_blx.target_address = target_address; + instruction->info.branch.reg_operand = -1; + instruction->info.branch.target_address = target_address; return ERROR_OK; } @@ -1430,8 +1430,8 @@ static int evaluate_misc_instr(uint32_t opcode, snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBX%s r%i", address, opcode, COND(opcode), Rm); - instruction->info.b_bl_bx_blx.reg_operand = Rm; - instruction->info.b_bl_bx_blx.target_address = -1; + instruction->info.branch.reg_operand = Rm; + instruction->info.branch.target_address = -1; } /* BXJ - "Jazelle" support (ARMv5-J) */ @@ -1444,8 +1444,8 @@ static int evaluate_misc_instr(uint32_t opcode, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBXJ%s r%i", address, opcode, COND(opcode), Rm); - instruction->info.b_bl_bx_blx.reg_operand = Rm; - instruction->info.b_bl_bx_blx.target_address = -1; + instruction->info.branch.reg_operand = Rm; + instruction->info.branch.target_address = -1; } /* CLZ */ @@ -1474,8 +1474,8 @@ static int evaluate_misc_instr(uint32_t opcode, snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBLX%s r%i", address, opcode, COND(opcode), Rm); - instruction->info.b_bl_bx_blx.reg_operand = Rm; - instruction->info.b_bl_bx_blx.target_address = -1; + instruction->info.branch.reg_operand = Rm; + instruction->info.branch.target_address = -1; } /* Enhanced DSP add/subtracts */ @@ -2110,8 +2110,8 @@ static int evaluate_b_bl_blx_thumb(uint16_t opcode, "0x%8.8" PRIx32 " 0x%4.4x \t%s\t%#8.8" PRIx32, address, opcode, mnemonic, target_address); - instruction->info.b_bl_bx_blx.reg_operand = -1; - instruction->info.b_bl_bx_blx.target_address = target_address; + instruction->info.branch.reg_operand = -1; + instruction->info.branch.target_address = target_address; return ERROR_OK; } @@ -2286,7 +2286,7 @@ static int evaluate_data_proc_thumb(uint16_t opcode, break; case 0x3: if ((opcode & 0x7) == 0x0) { - instruction->info.b_bl_bx_blx.reg_operand = Rm; + instruction->info.branch.reg_operand = Rm; if (H1) { instruction->type = ARM_BLX; snprintf(instruction->text, 128, @@ -2746,8 +2746,8 @@ static int evaluate_cond_branch_thumb(uint16_t opcode, arm_condition_strings[cond], target_address); instruction->type = ARM_B; - instruction->info.b_bl_bx_blx.reg_operand = -1; - instruction->info.b_bl_bx_blx.target_address = target_address; + instruction->info.branch.reg_operand = -1; + instruction->info.branch.target_address = target_address; return ERROR_OK; } @@ -3049,8 +3049,8 @@ static int t2ev_b_bl(uint32_t opcode, uint32_t address, default: return ERROR_COMMAND_SYNTAX_ERROR; } - instruction->info.b_bl_bx_blx.reg_operand = -1; - instruction->info.b_bl_bx_blx.target_address = address; + instruction->info.branch.reg_operand = -1; + instruction->info.branch.target_address = address; sprintf(cp, "%s\t%#8.8" PRIx32, inst, address); return ERROR_OK; @@ -3085,8 +3085,8 @@ static int t2ev_cond_b(uint32_t opcode, uint32_t address, address += offset << 1; instruction->type = ARM_B; - instruction->info.b_bl_bx_blx.reg_operand = -1; - instruction->info.b_bl_bx_blx.target_address = address; + instruction->info.branch.reg_operand = -1; + instruction->info.branch.target_address = address; sprintf(cp, "B%s.W\t%#8.8" PRIx32, arm_condition_strings[cond], address); diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h index 486e903..acbc0b3 100644 --- a/src/target/arm_disassembler.h +++ b/src/target/arm_disassembler.h @@ -123,7 +123,7 @@ enum arm_instruction_type { ARM_UNDEFINED_INSTRUCTION = 0xffffffff, }; -struct arm_b_bl_bx_blx_instr { +struct arm_branch_instr { int reg_operand; uint32_t target_address; }; @@ -185,7 +185,7 @@ struct arm_instruction { unsigned instruction_size; union { - struct arm_b_bl_bx_blx_instr b_bl_bx_blx; + struct arm_branch_instr branch; struct arm_data_proc_instr data_proc; struct arm_load_store_instr load_store; struct arm_load_store_multiple_instr load_store_multiple; diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c index 245e108..ac6177e 100644 --- a/src/target/arm_simulator.c +++ b/src/target/arm_simulator.c @@ -290,14 +290,14 @@ static int arm_simulate_step_core(struct target *target, /* Deal with 32-bit BL/BLX */ if ((opcode & 0xf800) == 0xf000) { - uint32_t high = instruction.info.b_bl_bx_blx.target_address; + uint32_t high = instruction.info.branch.target_address; retval = target_read_u16(target, current_pc+2, &opcode); if (retval != ERROR_OK) return retval; retval = thumb_evaluate_opcode(opcode, current_pc, &instruction); if (retval != ERROR_OK) return retval; - instruction.info.b_bl_bx_blx.target_address += high; + instruction.info.branch.target_address += high; } } @@ -307,12 +307,12 @@ static int arm_simulate_step_core(struct target *target, if ((instruction.type >= ARM_B) && (instruction.type <= ARM_BLX)) { uint32_t target_address; - if (instruction.info.b_bl_bx_blx.reg_operand == -1) - target_address = instruction.info.b_bl_bx_blx.target_address; + if (instruction.info.branch.reg_operand == -1) + target_address = instruction.info.branch.target_address; else { target_address = sim->get_reg_mode(sim, - instruction.info.b_bl_bx_blx.reg_operand); - if (instruction.info.b_bl_bx_blx.reg_operand == 15) + instruction.info.branch.reg_operand); + if (instruction.info.branch.reg_operand == 15) target_address += 2 * instruction_size; } diff --git a/src/target/etm.c b/src/target/etm.c index 5d079ff..65ec5c1 100644 --- a/src/target/etm.c +++ b/src/target/etm.c @@ -1106,8 +1106,8 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_invocatio if (((instruction.type == ARM_B) || (instruction.type == ARM_BL) || (instruction.type == ARM_BLX)) && - (instruction.info.b_bl_bx_blx.target_address != 0xffffffff)) - next_pc = instruction.info.b_bl_bx_blx.target_address; + (instruction.info.branch.target_address != 0xffffffff)) + next_pc = instruction.info.branch.target_address; else next_pc += (ctx->core_state == ARM_STATE_ARM) ? 4 : 2; } else if (pipestat == STAT_IN) diff --git a/src/target/xscale.c b/src/target/xscale.c index 770b325..2b1a20e 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -2799,7 +2799,7 @@ static int xscale_analyze_trace(struct target *target, struct command_invocation if ((trace_msg_type == 8) || (trace_msg_type == 12)) { retval = xscale_read_instruction(target, current_pc, &instruction); if (retval == ERROR_OK) - current_pc = instruction.info.b_bl_bx_blx.target_address; + current_pc = instruction.info.branch.target_address; else current_pc = 0; /* branch destination unknown */ -- _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
