This is an automated email from Gerrit. Tarek BOCHKATI ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/5796
-- gerrit commit 275976ef89a62a664fba9d2cfe6a9a14829b3660 Author: Tarek BOCHKATI <[email protected]> Date: Tue Aug 11 12:06:58 2020 +0100 arm_disassembler: add armv8-m new branch instructions bxns, blxns Change-Id: I2501b53fd3486bf9dc36bfe3119b6c45d1293dee Signed-off-by: Laurent LEMELE <[email protected]> Signed-off-by: Tarek BOCHKATI <[email protected]> diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c index 5be4c46..d361861 100644 --- a/src/target/arm_disassembler.c +++ b/src/target/arm_disassembler.c @@ -2300,6 +2300,21 @@ static int evaluate_data_proc_thumb(uint16_t opcode, " 0x%4.4x \tBX\tr%i", address, opcode, Rm); } + } else if ((opcode & 0x7) == 0x4) { + instruction->info.branch.reg_operand = Rm; + if (H1) { + instruction->type = ARM_BLXNS; + snprintf(instruction->text, 128, + "0x%8.8" PRIx32 + " 0x%4.4x \tBLXNS\tr%i", + address, opcode, Rm); + } else { + instruction->type = ARM_BXNS; + snprintf(instruction->text, 128, + "0x%8.8" PRIx32 + " 0x%4.4x \tBXNS\tr%i", + address, opcode, Rm); + } } else { instruction->type = ARM_UNDEFINED_INSTRUCTION; snprintf(instruction->text, 128, diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h index acbc0b3..2740639 100644 --- a/src/target/arm_disassembler.h +++ b/src/target/arm_disassembler.h @@ -26,7 +26,9 @@ enum arm_instruction_type { ARM_B, ARM_BL, ARM_BX, + ARM_BXNS, ARM_BLX, + ARM_BLXNS, /* Data processing instructions */ ARM_AND, -- _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
