This is an automated email from Gerrit. Adrian M Negreanu ([email protected]) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/5805
-- gerrit commit 0a377809a099266629ce4c913941aa412685da2d Author: Adrian Negreanu <[email protected]> Date: Fri Aug 14 22:20:52 2020 +0300 target/armv7m: add a configurable TPI base address The TPIU address mentioned in ARM specs is 0xE0040000. In case the TPIU is shared, it can be mapped at a different address. Change-Id: I7c4041636e0df7623e1758905c5fbb9db294c422 Signed-off-by: Adrian Negreanu <[email protected]> diff --git a/src/target/armv7m_trace.c b/src/target/armv7m_trace.c index 6b368f7..ba7c598 100644 --- a/src/target/armv7m_trace.c +++ b/src/target/armv7m_trace.c @@ -89,27 +89,27 @@ int armv7m_trace_tpiu_config(struct target *target) return ERROR_FAIL; } - retval = target_write_u32(target, TPIU_CSPSR, 1 << trace_config->port_size); + retval = target_write_u32(target, TPIU_CSPSR(trace_config->tpiu_baseaddr), 1 << trace_config->port_size); if (retval != ERROR_OK) return retval; - retval = target_write_u32(target, TPIU_ACPR, prescaler - 1); + retval = target_write_u32(target, TPIU_ACPR(trace_config->tpiu_baseaddr), prescaler - 1); if (retval != ERROR_OK) return retval; - retval = target_write_u32(target, TPIU_SPPR, trace_config->pin_protocol); + retval = target_write_u32(target, TPIU_SPPR(trace_config->tpiu_baseaddr), trace_config->pin_protocol); if (retval != ERROR_OK) return retval; uint32_t ffcr; - retval = target_read_u32(target, TPIU_FFCR, &ffcr); + retval = target_read_u32(target, TPIU_FFCR(trace_config->tpiu_baseaddr), &ffcr); if (retval != ERROR_OK) return retval; if (trace_config->formatter) ffcr |= (1 << 1); else ffcr &= ~(1 << 1); - retval = target_write_u32(target, TPIU_FFCR, ffcr); + retval = target_write_u32(target, TPIU_FFCR(trace_config->tpiu_baseaddr), ffcr); if (retval != ERROR_OK) return retval; @@ -165,6 +165,7 @@ COMMAND_HANDLER(handle_tpiu_config_command) struct armv7m_common *armv7m = target_to_armv7m(target); unsigned int cmd_idx = 0; + armv7m->trace_config.tpiu_baseaddr = TPIU_BASEADDR; if (CMD_ARGC == cmd_idx) return ERROR_COMMAND_SYNTAX_ERROR; @@ -202,6 +203,17 @@ COMMAND_HANDLER(handle_tpiu_config_command) if (CMD_ARGC == cmd_idx) return ERROR_COMMAND_SYNTAX_ERROR; + if (!strcmp(CMD_ARGV[cmd_idx], "baseaddr")) { + cmd_idx++; + if (CMD_ARGC == cmd_idx) + return ERROR_COMMAND_SYNTAX_ERROR; + + COMMAND_PARSE_ADDRESS(CMD_ARGV[cmd_idx], armv7m->trace_config.tpiu_baseaddr); + } + + cmd_idx++; + if (CMD_ARGC == cmd_idx) + return ERROR_COMMAND_SYNTAX_ERROR; if (!strcmp(CMD_ARGV[cmd_idx], "sync")) { armv7m->trace_config.pin_protocol = TPIU_PIN_PROTOCOL_SYNC; @@ -308,6 +320,7 @@ static const struct command_registration tpiu_command_handlers[] = { .usage = "(disable | " "((external | internal <filename>) " "(sync <port width> | ((manchester | uart) <formatter enable>)) " + "(baseaddr <base address>)" "<TRACECLKIN freq> [<trace freq>]))", }, COMMAND_REGISTRATION_DONE diff --git a/src/target/armv7m_trace.h b/src/target/armv7m_trace.h index e5879fb..add932a 100644 --- a/src/target/armv7m_trace.h +++ b/src/target/armv7m_trace.h @@ -75,6 +75,8 @@ struct armv7m_trace_config { unsigned int trace_freq; /** Handle to output trace data in INTERNAL capture mode */ FILE *trace_file; + /** Base Address for the TPIU */ + target_addr_t tpiu_baseaddr; }; extern const struct command_registration armv7m_trace_command_handlers[]; diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h index a767f93..448f969 100644 --- a/src/target/cortex_m.h +++ b/src/target/cortex_m.h @@ -79,13 +79,23 @@ #define FPU_FPCAR 0xE000EF38 #define FPU_FPDSCR 0xE000EF3C -#define TPIU_SSPSR 0xE0040000 -#define TPIU_CSPSR 0xE0040004 -#define TPIU_ACPR 0xE0040010 -#define TPIU_SPPR 0xE00400F0 -#define TPIU_FFSR 0xE0040300 -#define TPIU_FFCR 0xE0040304 -#define TPIU_FSCR 0xE0040308 +#define TPIU_BASEADDR 0xE0040000 + +#define TPIU_OFFSET_SSPSR 0x000 +#define TPIU_OFFSET_CSPSR 0x004 +#define TPIU_OFFSET_ACPR 0x010 +#define TPIU_OFFSET_SSPR 0x0F0 +#define TPIU_OFFSET_FFSR 0x300 +#define TPIU_OFFSET_FFCR 0x304 +#define TPIU_OFFSET_FSCR 0x308 + +#define TPIU_SSPSR(base) ((base)+TPIU_OFFSET_SSPSR) +#define TPIU_CSPSR(base) ((base)+TPIU_OFFSET_CSPSR) +#define TPIU_ACPR(base) ((base)+TPIU_OFFSET_ACPR) +#define TPIU_SPPR(base) ((base)+TPIU_OFFSET_SSPR) +#define TPIU_FFSR(base) ((base)+TPIU_OFFSET_FFSR) +#define TPIU_FFCR(base) ((base)+TPIU_OFFSET_FFCR) +#define TPIU_FSCR(base) ((base)+TPIU_OFFSET_FSCR) /* Maximum SWO prescaler value. */ #define TPIU_ACPR_MAX_SWOSCALER 0x1fff -- _______________________________________________ OpenOCD-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/openocd-devel
