This is an automated email from Gerrit.
"Nishanth Menon <n...@ti.com>" just uploaded a new patch set to Gerrit, which
you can find at https://review.openocd.org/c/openocd/+/6798
-- gerrit
commit 796c812d3e3c442a1e97252b12467d80f580232a
Author: Nishanth Menon <n...@ti.com>
Date: Mon Jan 3 13:23:38 2022 -0600
tcl/target/ti_k3: Add AM625 SoC
Add support for the latest in TI k3 family AM625 SoC.
For further details, see https://www.ti.com/lit/pdf/spruiv7
Signed-off-by: Nishanth Menon <n...@ti.com>
Change-Id: Ia54d0eab1c30a973afb1c2c61f4c5a72d29d9b78
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 9f9fbf388..889c4c81b 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -97,6 +97,36 @@ switch $_soc {
# M4 processor
set _gp_mcu_cores 1
}
+ am625 {
+ set _CHIPNAME am625
+ set _K3_DAP_TAPID 0x0bb7e02f
+
+ # AM625 has 1 clusters of 4 A53 cores.
+ set _armv8_cpu_name a53
+ set _armv8_cores 4
+ set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
+ set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
+
+ # AM642 has 1 cluster of 1 R5s core.
+ set _r5_cores 1
+ set _mcu_r5_cores 0
+ set _mcu_base_core_id 0
+ set _main0_r5_cores 1
+ set _main0_base_core_id 0
+ set _main1_r5_cores 0
+ set _main1_base_core_id 0
+ set R5_DBGBASE {0x9d410000}
+ set R5_CTIBASE {0x9d418000}
+
+ # sysctrl CTI base
+ set CM3_CTIBASE {0x20001000}
+ # Sysctrl power-ap unlock offsets
+ set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+
+ # M4 processor
+ set _gp_mcu_cores 1
+ set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
+ }
j721e {
set _CHIPNAME j721e
set _K3_DAP_TAPID 0x0bb6402f
--
