This is an automated email from Gerrit.
"Nishanth Menon <n...@ti.com>" just uploaded a new patch set to Gerrit, which
you can find at https://review.openocd.org/c/openocd/+/6796
-- gerrit
commit 8cb59267db2d5c1bd762f6b4f32e9df7323f2122
Author: Nishanth Menon <n...@ti.com>
Date: Thu Oct 14 09:55:49 2021 -0500
tcl/target/ti_k3: Add J721S2 SoC
Add support for the latest in TI k3 family J721S2 SoC.
For further details, see http://www.ti.com/lit/pdf/spruj28
Signed-off-by: Nishanth Menon <n...@ti.com>
Change-Id: I608ab4513ffb6b5c4166ba423e7d0dddbbb3bbfd
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 9775b750a..9f9fbf388 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -135,6 +135,32 @@ switch $_soc {
# M3 CTI base
set CM3_CTIBASE {0x20001000}
}
+ j721s2 {
+ set _CHIPNAME j721s2
+ set _K3_DAP_TAPID 0x0bb7502f
+
+ # J721s2 has 1 cluster of 2 A72 cores.
+ set _armv8_cpu_name a72
+ set _armv8_cores 2
+
+ # J721s2 has 3 clusters of 2 R5 cores each.
+ set _r5_cores 6
+ set _mcu_r5_cores 2
+ set _mcu_base_core_id 0
+ set _main0_r5_cores 2
+ set _main0_base_core_id 2
+ set _main1_r5_cores 2
+ set _main1_base_core_id 4
+
+ # sysctrl CTI base
+ set CM3_CTIBASE {0x20001000}
+ # Sysctrl power-ap unlock offsets
+ set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+
+ # M4 processor
+ set _gp_mcu_cores 1
+ set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
+ }
default {
echo "'$_soc' is invalid!"
}
--
