This is an automated email from Gerrit.

"Wren Turkal <w...@penguintechs.org>" just uploaded a new patch set to Gerrit, 
which you can find at https://review.openocd.org/c/openocd/+/6800

-- gerrit

commit a36c678727fcb2edd7fbc8aed6c2773969897095
Author: Wren Turkal <w...@penguintechs.org>
Date:   Tue Jan 4 23:30:18 2022 -0800

    Initial cut at support for LPC55S16.
    
    This will allow the LPC55S16 device to be debugged with openocd.
    
    Signed-off-by: Wren Turkal <w...@penguintechs.org>
    Change-Id: Icbe234801a386963725d5923d6860d15138e09bf

diff --git a/tcl/target/lpc55s16.cfg b/tcl/target/lpc55s16.cfg
new file mode 100644
index 000000000..f82098254
--- /dev/null
+++ b/tcl/target/lpc55s16.cfg
@@ -0,0 +1,66 @@
+source [find target/swj-dp.tcl]
+
+adapter speed 4294967295
+
+if { [info exists CHIPNAME] } {
+       set _CHIPNAME $CHIPNAME
+} else {
+       set _CHIPNAME lpc55s16
+}
+
+#
+# JTAG mode TAP
+#
+if { [info exists M33_JTAG_TAPID] } {
+       set _JTAG_TAPID $M33_JTAG_TAPID
+} else {
+       set _JTAG_TAPID 0x4ba00477
+}
+
+#
+# SWD mode TAP
+#
+if { [info exists M33_SWD_TAPID] } {
+       set _SWD_TAPID $M33_SWD_TAPID
+} else {
+#      set _SWD_TAPID 0x2ba01477
+       set _SWD_TAPID 0x0be12477
+}
+
+if { [using_jtag] } {
+       set _CPUTAPID $_JTAG_TAPID
+} {
+       set _CPUTAPID $_SWD_TAPID
+}
+
+##
+## M0 TAP
+##
+#if { [info exists M0_JTAG_TAPID] } {
+#      set _M0_JTAG_TAPID $M0_JTAG_TAPID
+#} else {
+#      set _M0_JTAG_TAPID 0x0ba01477
+#}
+
+swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
+                               -expected-id $_CPUTAPID
+dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
+target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
+
+# LPCSSS16-EVK has 256+96 KB SRAM
+if { [info exists WORKAREASIZE] } {
+       set _WORKAREASIZE $WORKAREASIZE
+} else {
+       set _WORKAREASIZE 0x98000
+}
+$_CHIPNAME.m4 configure -work-area-phys 0x10000000 \
+                       -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+#if {![using_hla]} {
+#   # on this CPU we should use VECTRESET to perform a soft reset and
+#   # manually reset the periphery
+#   # SRST or SYSRESETREQ disable the debug interface for the time of
+#   # the reset and will not fit our requirements for a consistent debug
+#   # session
+#   cortex_m reset_config vectreset
+#}

-- 

Reply via email to