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"Name of user not set <sean.ander...@seco.com>" just uploaded a new patch set
to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/6854
-- gerrit
commit 7b510c1cc2d4d1e4d7639070b2de2687883107a5
Author: Sean Anderson <sean.ander...@seco.com>
Date: Mon Feb 21 14:06:51 2022 -0500
target: Add LS1046A
The LS1046A is a quad-core processor from NXP in the layerscape family.
This SoC is a bit tricky to program: while the AArch64 CPUs are
little-endian, most of the peripherals are big-endian. Care must be
taken when interpreting memory reads/writes. This processor is in the
same family as the ls1012a, so the setup is similar.
A "release_cpu" procedure is provided for releasing CPUs when booting
using a hard-coded RCW. The byte-swap is a bit overkill :)
Signed-off-by: Sean Anderson <sean.ander...@seco.com>
Change-Id: If5a1a9441fb35fea3e05dc708b42e0cb3bbf2a54
diff --git a/tcl/target/ls1046a.cfg b/tcl/target/ls1046a.cfg
new file mode 100644
index 000000000..958d1a387
--- /dev/null
+++ b/tcl/target/ls1046a.cfg
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# NXP LS1046A
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME ls1046a
+}
+
+if { [info exists DAP_TAPID] } {
+ set _DAP_TAPID $DAP_TAPID
+} else {
+ set _DAP_TAPID 0x5ba00477
+}
+
+if { [info exists SAP_TAPID] } {
+ set _SAP_TAPID $SAP_TAPID
+} else {
+ set _SAP_TAPID 0x06b3001d
+}
+
+jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
+
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+set _CPU_BASE 0x80400000
+set _CPU_STRIDE 0x100000
+set _CPU_DBGOFF 0x10000
+set _CPU_CTIOFF 0x20000
+
+set _TARGETS {}
+for {set i 0} {$i < 4} {incr i} {
+ set _BASE [expr {$_CPU_BASE + $_CPU_STRIDE * $i}]
+ cti create $_CHIPNAME.cti$i -dap $_CHIPNAME.dap -ap-num 1 \
+ -baseaddr [expr {$_BASE + $_CPU_CTIOFF}]
+ target create $_CHIPNAME.cpu$i aarch64 -dap $_CHIPNAME.dap \
+ -cti $_CHIPNAME.cti$i -dbgbase [expr {$_BASE + $_CPU_DBGOFF}] \
+ -coreid $i {*}[expr {$i ? {} : "-rtos hwthread" }]
+ lappend _TARGETS $_CHIPNAME.cpu$i
+}
+
+target smp {*}$_TARGETS
+
+jtag newtap $_CHIPNAME sap -irlen 8 -expected-id $_SAP_TAPID
+target create $_CHIPNAME.sap ls1_sap -chain-position $_CHIPNAME.sap -endian big
+
+# Normally you will not need to call this, but if you are using the hard-coded
+# Reset Configuration Word (RCW) you will need to call this manually. The CPU
+# will begin executing at the address specified by SCFG_SCRATCHRW1/2. NOTE:
+# these registers are big endian.
+#
+# This code is idempotent; releasing a released CPU has no effect.
+add_help_text release_cpu "Release CPUs which are held off"
+proc release_cpu {args} {
+ set DCFG_BRR 0x1ee00e4
+
+ set val 0
+ foreach core $args {
+ set val [expr {$val | 1 << $core}]
+ }
+ # The DCFG is big-endian, so we need to swap the bytes
+ set val [expr {
+ ($val >> 24) |
+ (($val >> 8) & 0xff00) |
+ (($val << 8) & 0xff0000) |
+ (($val & 0xff) << 24)
+ }]
+
+ $::_CHIPNAME.sap mem2array regs 32 $DCFG_BRR 1
+ $::_CHIPNAME.sap mww $DCFG_BRR [expr {$regs(0) | $val}]
+}
+
+targets $_CHIPNAME.cpu0
+
+adapter speed 10000
--
