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"Erhan Kurubas <erhan.kuru...@espressif.com>" just uploaded a new patch set to 
Gerrit, which you can find at https://review.openocd.org/c/openocd/+/7037

-- gerrit

commit 831a00cd64aad3e188341792919102ac49241b80
Author: Erhan Kurubas <erhan.kuru...@espressif.com>
Date:   Sat Jun 18 23:16:37 2022 +0200

    tcl/esp32s3: check memory protection on gdb attach
    
    Memory protection must be disabled to allow stub flasher
    operate correctly.
    
    Signed-off-by: Erhan Kurubas <erhan.kuru...@espressif.com>
    Change-Id: I6f292ee672ae001cd6e4df5d24eb7bb862639093

diff --git a/tcl/target/esp32s3.cfg b/tcl/target/esp32s3.cfg
index 0570501c75..2ca0ad855d 100644
--- a/tcl/target/esp32s3.cfg
+++ b/tcl/target/esp32s3.cfg
@@ -39,7 +39,50 @@ if { $_ONLYCPU != 1 } {
 }
 
 proc esp32s3_memprot_is_enabled { } {
-       # TODO: after https://review.openocd.org/c/openocd/+/7016 merged
+       # SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
+       if { [get_mmr_bit 0x600C10C0 0] != 0 } {
+               return 1
+       }
+       # SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
+       if { [get_mmr_bit 0x600C1124 0] != 0 } {
+               return 1
+       }
+       # SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG
+       if { [get_mmr_bit 0x600C11D0 0] != 0 } {
+               return 1
+       }
+       # IRAM0, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
+       if { [get_mmr_bit 0x600C10D8 0] != 0 } {
+               return 1
+       }
+       # DRAM0, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
+       if { [get_mmr_bit 0x600C10FC 0] != 0 } {
+               return 1
+       }
+       # SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
+       if { [get_mmr_bit 0x600C10E4 0] != 0 } {
+               return 1
+       }
+       # SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG
+       if { [get_mmr_bit 0x600C10F0 0] != 0 } {
+               return 1
+       }
+       # SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
+       if { [get_mmr_bit 0x600C1104 0] != 0 } {
+               return 1
+       }
+       # SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG
+       if { [get_mmr_bit 0x600C1114 0] != 0 } {
+               return 1
+       }
+       # SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
+       if { [get_mmr_bit 0x600C119C 0] != 0 } {
+               return 1
+       }
+       # SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG
+       if { [get_mmr_bit 0x600C1248 0] != 0 } {
+               return 1
+       }
        return 0
 }
 

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