[PATCH]: 56064ae16d target/xtensa: invalidate register cache on reset

[gerrit]

This is an automated email from Gerrit.

"Ian Thompson <ia...@cadence.com>" just uploaded a new patch set to Gerrit, 
which you can find at https://review.openocd.org/c/openocd/+/7197

-- gerrit

commit 56064ae16db07205f6a98fb9e8609ee45c48428f
Author: Ian Thompson <ia...@cadence.com>
Date:   Thu Sep 15 14:14:15 2022 -0700

    target/xtensa: invalidate register cache on reset
    
    Resolves issues where registers are accessed when poll() logic is inactive 
or has not yet been triggered.
    
    Signed-off-by: Ian Thompson <ia...@cadence.com>
    Change-Id: If7a4d00938fb188b008325249627f7773c3484c5

diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index f331a86654..926d49303b 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -956,7 +956,6 @@ int xtensa_assert_reset(struct target *target)
        struct xtensa *xtensa = target_to_xtensa(target);
 
        LOG_TARGET_DEBUG(target, "target_number=%i, begin", 
target->target_number);
-       target->state = TARGET_RESET;
        xtensa_queue_pwr_reg_write(xtensa,
                XDMREG_PWRCTL,
                PWRCTL_JTAGDEBUGUSE(xtensa) | PWRCTL_DEBUGWAKEUP(xtensa) | 
PWRCTL_MEMWAKEUP(xtensa) |
@@ -965,8 +964,12 @@ int xtensa_assert_reset(struct target *target)
        int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
        if (res != ERROR_OK)
                return res;
+
+       /* registers are now invalid */
        xtensa->reset_asserted = true;
-       return res;
+       register_cache_invalidate(xtensa->core_cache);
+       target->state = TARGET_RESET;
+       return ERROR_OK;
 }
 
 int xtensa_deassert_reset(struct target *target)

--